1 // SPDX-License-Identifier: GPL-2.0+ 2 3 #include <asm/arch/clock.h> 4 #include <asm/arch/iomux.h> 5 #include <asm/arch/imx-regs.h> 6 #include <asm/arch/crm_regs.h> 7 #include <asm/arch/mx6ul_pins.h> 8 #include <asm/arch/mx6-pins.h> 9 #include <asm/arch/sys_proto.h> 10 #include <asm/gpio.h> 11 #include <asm/mach-imx/iomux-v3.h> 12 #include <asm/mach-imx/boot_mode.h> 13 #include <linux/libfdt.h> 14 #include <spl.h> 15 16 #if defined(CONFIG_SPL_BUILD) 17 #include <asm/arch/mx6-ddr.h> 18 19 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 20 .grp_addds = 0x00000030, 21 .grp_ddrmode_ctl = 0x00020000, 22 .grp_b0ds = 0x00000030, 23 .grp_ctlds = 0x00000030, 24 .grp_b1ds = 0x00000030, 25 .grp_ddrpke = 0x00000000, 26 .grp_ddrmode = 0x00020000, 27 .grp_ddr_type = 0x00080000, 28 }; 29 30 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 31 .dram_dqm0 = 0x00000030, 32 .dram_dqm1 = 0x00000030, 33 .dram_ras = 0x00000030, 34 .dram_cas = 0x00000030, 35 .dram_odt0 = 0x00000030, 36 .dram_odt1 = 0x00000030, 37 .dram_sdba2 = 0x00000000, 38 .dram_sdclk_0 = 0x00000030, 39 .dram_sdqs0 = 0x00000030, 40 .dram_sdqs1 = 0x00000030, 41 .dram_reset = 0x00000030, 42 }; 43 44 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 45 .p0_mpwldectrl0 = 0x00000000, 46 .p0_mpdgctrl0 = 0x01380134, 47 .p0_mprddlctl = 0x40404244, 48 .p0_mpwrdlctl = 0x40405050, 49 }; 50 51 static struct mx6_ddr_sysinfo ddr_sysinfo = { 52 .dsize = 0, 53 .cs1_mirror = 0, 54 .cs_density = 32, 55 .ncs = 1, 56 .bi_on = 1, 57 .rtt_nom = 1, 58 .rtt_wr = 0, 59 .ralat = 5, 60 .walat = 0, 61 .mif3_mode = 3, 62 .rst_to_cke = 0x23, 63 .sde_to_rst = 0x10, 64 .refsel = 1, 65 .refr = 3, 66 }; 67 68 static struct mx6_ddr3_cfg mem_ddr = { 69 .mem_speed = 1333, 70 .density = 2, 71 .width = 16, 72 .banks = 8, 73 .rowaddr = 14, 74 .coladdr = 10, 75 .pagesz = 2, 76 .trcd = 1350, 77 .trcmin = 4950, 78 .trasmin = 3600, 79 }; 80 81 static void ccgr_init(void) 82 { 83 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 84 85 writel(0xFFFFFFFF, &ccm->CCGR0); 86 writel(0xFFFFFFFF, &ccm->CCGR1); 87 writel(0xFFFFFFFF, &ccm->CCGR2); 88 writel(0xFFFFFFFF, &ccm->CCGR3); 89 writel(0xFFFFFFFF, &ccm->CCGR4); 90 writel(0xFFFFFFFF, &ccm->CCGR5); 91 writel(0xFFFFFFFF, &ccm->CCGR6); 92 } 93 94 static void spl_dram_init(void) 95 { 96 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 97 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 98 } 99 100 void board_init_f(ulong dummy) 101 { 102 ccgr_init(); 103 arch_cpu_init(); 104 board_early_init_f(); 105 timer_init(); 106 preloader_console_init(); 107 spl_dram_init(); 108 memset(__bss_start, 0, __bss_end - __bss_start); 109 board_init_r(NULL, 0); 110 } 111 112 void reset_cpu(ulong addr) 113 { 114 } 115 #endif 116