1 // SPDX-License-Identifier: GPL-2.0+
2 
3 #include <asm/arch/clock.h>
4 #include <asm/arch/iomux.h>
5 #include <asm/arch/imx-regs.h>
6 #include <asm/arch/crm_regs.h>
7 #include <asm/arch/mx6ul_pins.h>
8 #include <asm/arch/mx6-pins.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/gpio.h>
11 #include <asm/mach-imx/iomux-v3.h>
12 #include <asm/mach-imx/boot_mode.h>
13 #include <linux/libfdt.h>
14 #include <spl.h>
15 
16 #if defined(CONFIG_SPL_BUILD)
17 
18 #ifdef CONFIG_SPL_OS_BOOT
19 int spl_start_uboot(void)
20 {
21 	return 0;
22 }
23 #endif
24 
25 #include <asm/arch/mx6-ddr.h>
26 
27 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
28 	.grp_addds = 0x00000030,
29 	.grp_ddrmode_ctl = 0x00020000,
30 	.grp_b0ds = 0x00000030,
31 	.grp_ctlds = 0x00000030,
32 	.grp_b1ds = 0x00000030,
33 	.grp_ddrpke = 0x00000000,
34 	.grp_ddrmode = 0x00020000,
35 	.grp_ddr_type = 0x00080000,
36 };
37 
38 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
39 	.dram_dqm0 = 0x00000030,
40 	.dram_dqm1 = 0x00000030,
41 	.dram_ras = 0x00000030,
42 	.dram_cas = 0x00000030,
43 	.dram_odt0 = 0x00000030,
44 	.dram_odt1 = 0x00000030,
45 	.dram_sdba2 = 0x00000000,
46 	.dram_sdclk_0 = 0x00000030,
47 	.dram_sdqs0 = 0x00000030,
48 	.dram_sdqs1 = 0x00000030,
49 	.dram_reset = 0x00000030,
50 };
51 
52 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
53 	.p0_mpwldectrl0 = 0x00000000,
54 	.p0_mpdgctrl0 = 0x01380134,
55 	.p0_mprddlctl = 0x40404244,
56 	.p0_mpwrdlctl = 0x40405050,
57 };
58 
59 static struct mx6_ddr_sysinfo ddr_sysinfo = {
60 	.dsize		= 0,
61 	.cs1_mirror	= 0,
62 	.cs_density	= 32,
63 	.ncs		= 1,
64 	.bi_on		= 1,
65 	.rtt_nom	= 1,
66 	.rtt_wr		= 0,
67 	.ralat		= 5,
68 	.walat		= 0,
69 	.mif3_mode	= 3,
70 	.rst_to_cke	= 0x23,
71 	.sde_to_rst	= 0x10,
72 	.refsel = 1,
73 	.refr = 3,
74 };
75 
76 static struct mx6_ddr3_cfg mem_ddr = {
77 	.mem_speed = 1333,
78 	.density = 2,
79 	.width = 16,
80 	.banks = 8,
81 	.coladdr = 10,
82 	.pagesz = 2,
83 	.trcd = 1350,
84 	.trcmin = 4950,
85 	.trasmin = 3600,
86 };
87 
88 static void ccgr_init(void)
89 {
90 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
91 
92 	writel(0xFFFFFFFF, &ccm->CCGR0);
93 	writel(0xFFFFFFFF, &ccm->CCGR1);
94 	writel(0xFFFFFFFF, &ccm->CCGR2);
95 	writel(0xFFFFFFFF, &ccm->CCGR3);
96 	writel(0xFFFFFFFF, &ccm->CCGR4);
97 	writel(0xFFFFFFFF, &ccm->CCGR5);
98 	writel(0xFFFFFFFF, &ccm->CCGR6);
99 }
100 
101 static void imx6ul_spl_dram_cfg_size(u32 ram_size)
102 {
103 	if (ram_size == SZ_256M)
104 		mem_ddr.rowaddr = 14;
105 	else
106 		mem_ddr.rowaddr = 15;
107 
108 	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
109 	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
110 }
111 
112 static void imx6ul_spl_dram_cfg(void)
113 {
114 	ulong ram_size_test, ram_size = 0;
115 
116 	for (ram_size = SZ_512M; ram_size >= SZ_256M; ram_size >>= 1) {
117 		imx6ul_spl_dram_cfg_size(ram_size);
118 		ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
119 		if (ram_size_test == ram_size)
120 			break;
121 	}
122 
123 	if (ram_size < SZ_256M) {
124 		puts("ERROR: DRAM size detection failed\n");
125 		hang();
126 	}
127 }
128 
129 void board_init_f(ulong dummy)
130 {
131 	ccgr_init();
132 	arch_cpu_init();
133 	board_early_init_f();
134 	timer_init();
135 	preloader_console_init();
136 	imx6ul_spl_dram_cfg();
137 	memset(__bss_start, 0, __bss_end - __bss_start);
138 	board_init_r(NULL, 0);
139 }
140 
141 void reset_cpu(ulong addr)
142 {
143 }
144 #endif
145