1 // SPDX-License-Identifier: GPL-2.0+
2 
3 #include <asm/arch/clock.h>
4 #include <asm/arch/iomux.h>
5 #include <asm/arch/imx-regs.h>
6 #include <asm/arch/crm_regs.h>
7 #include <asm/arch/mx6ul_pins.h>
8 #include <asm/arch/mx6-pins.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/gpio.h>
11 #include <asm/mach-imx/iomux-v3.h>
12 #include <asm/mach-imx/boot_mode.h>
13 #include <fsl_esdhc.h>
14 #include <linux/libfdt.h>
15 #include <spl.h>
16 
17 #if defined(CONFIG_SPL_BUILD)
18 
19 #ifdef CONFIG_SPL_OS_BOOT
20 int spl_start_uboot(void)
21 {
22 	return 0;
23 }
24 #endif
25 
26 #include <asm/arch/mx6-ddr.h>
27 
28 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
29 	.grp_addds = 0x00000030,
30 	.grp_ddrmode_ctl = 0x00020000,
31 	.grp_b0ds = 0x00000030,
32 	.grp_ctlds = 0x00000030,
33 	.grp_b1ds = 0x00000030,
34 	.grp_ddrpke = 0x00000000,
35 	.grp_ddrmode = 0x00020000,
36 	.grp_ddr_type = 0x00080000,
37 };
38 
39 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
40 	.dram_dqm0 = 0x00000030,
41 	.dram_dqm1 = 0x00000030,
42 	.dram_ras = 0x00000030,
43 	.dram_cas = 0x00000030,
44 	.dram_odt0 = 0x00000030,
45 	.dram_odt1 = 0x00000030,
46 	.dram_sdba2 = 0x00000000,
47 	.dram_sdclk_0 = 0x00000030,
48 	.dram_sdqs0 = 0x00000030,
49 	.dram_sdqs1 = 0x00000030,
50 	.dram_reset = 0x00000030,
51 };
52 
53 static struct mx6_mmdc_calibration mx6_mmcd_calib = {
54 	.p0_mpwldectrl0 = 0x00000000,
55 	.p0_mpdgctrl0 = 0x01380134,
56 	.p0_mprddlctl = 0x40404244,
57 	.p0_mpwrdlctl = 0x40405050,
58 };
59 
60 static struct mx6_ddr_sysinfo ddr_sysinfo = {
61 	.dsize		= 0,
62 	.cs1_mirror	= 0,
63 	.cs_density	= 32,
64 	.ncs		= 1,
65 	.bi_on		= 1,
66 	.rtt_nom	= 1,
67 	.rtt_wr		= 0,
68 	.ralat		= 5,
69 	.walat		= 0,
70 	.mif3_mode	= 3,
71 	.rst_to_cke	= 0x23,
72 	.sde_to_rst	= 0x10,
73 	.refsel = 1,
74 	.refr = 3,
75 };
76 
77 static struct mx6_ddr3_cfg mem_ddr = {
78 	.mem_speed = 1333,
79 	.density = 2,
80 	.width = 16,
81 	.banks = 8,
82 	.coladdr = 10,
83 	.pagesz = 2,
84 	.trcd = 1350,
85 	.trcmin = 4950,
86 	.trasmin = 3600,
87 };
88 
89 static void ccgr_init(void)
90 {
91 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
92 
93 	writel(0xFFFFFFFF, &ccm->CCGR0);
94 	writel(0xFFFFFFFF, &ccm->CCGR1);
95 	writel(0xFFFFFFFF, &ccm->CCGR2);
96 	writel(0xFFFFFFFF, &ccm->CCGR3);
97 	writel(0xFFFFFFFF, &ccm->CCGR4);
98 	writel(0xFFFFFFFF, &ccm->CCGR5);
99 	writel(0xFFFFFFFF, &ccm->CCGR6);
100 }
101 
102 static void imx6ul_spl_dram_cfg_size(u32 ram_size)
103 {
104 	if (ram_size == SZ_256M)
105 		mem_ddr.rowaddr = 14;
106 	else
107 		mem_ddr.rowaddr = 15;
108 
109 	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
110 	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
111 }
112 
113 static void imx6ul_spl_dram_cfg(void)
114 {
115 	ulong ram_size_test, ram_size = 0;
116 
117 	for (ram_size = SZ_512M; ram_size >= SZ_256M; ram_size >>= 1) {
118 		imx6ul_spl_dram_cfg_size(ram_size);
119 		ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
120 		if (ram_size_test == ram_size)
121 			break;
122 	}
123 
124 	if (ram_size < SZ_256M) {
125 		puts("ERROR: DRAM size detection failed\n");
126 		hang();
127 	}
128 }
129 
130 void board_init_f(ulong dummy)
131 {
132 	ccgr_init();
133 	arch_cpu_init();
134 	board_early_init_f();
135 	timer_init();
136 	preloader_console_init();
137 	imx6ul_spl_dram_cfg();
138 	memset(__bss_start, 0, __bss_end - __bss_start);
139 	board_init_r(NULL, 0);
140 }
141 
142 void reset_cpu(ulong addr)
143 {
144 }
145 
146 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
147 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
148 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
149 
150 static iomux_v3_cfg_t const usdhc1_pads[] = {
151 	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
154 	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
155 	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
156 	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
157 	MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
158 	MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
159 	MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 	MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 };
162 
163 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
164 	{USDHC1_BASE_ADDR},
165 };
166 
167 int board_mmc_getcd(struct mmc *mmc)
168 {
169 	return 1;
170 }
171 
172 int board_mmc_init(bd_t *bis)
173 {
174 	imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
175 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
176 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
177 }
178 #endif
179