1 /*
2  * Copyright (C) 2015 Technexion Ltd.
3  *
4  * Author: Richard Hu <richard.hu@technexion.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <asm/arch/clock.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/gpio.h>
16 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/io.h>
18 #include <common.h>
19 #include <fsl_esdhc.h>
20 #include <linux/sizes.h>
21 #include <usb.h>
22 
23 DECLARE_GLOBAL_DATA_PTR;
24 
25 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
26 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
27 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
28 
29 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
30 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
31 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
32 
33 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
34 	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
35 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
36 
37 int dram_init(void)
38 {
39 	gd->ram_size = imx_ddr_size();
40 
41 	return 0;
42 }
43 
44 static iomux_v3_cfg_t const uart6_pads[] = {
45 	MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
46 	MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
47 };
48 
49 static iomux_v3_cfg_t const usdhc1_pads[] = {
50 	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
51 	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
52 	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
53 	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
54 	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
55 	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
56 	MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
57 	MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
58 	MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 	MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
60 };
61 
62 static iomux_v3_cfg_t const usb_otg_pad[] = {
63 	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
64 };
65 
66 static void setup_iomux_uart(void)
67 {
68 	imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
69 }
70 
71 static void setup_usb(void)
72 {
73 	imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad));
74 }
75 
76 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
77 	{USDHC1_BASE_ADDR},
78 };
79 
80 int board_mmc_getcd(struct mmc *mmc)
81 {
82 	return 1;
83 }
84 
85 int board_mmc_init(bd_t *bis)
86 {
87 	imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
88 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
89 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
90 }
91 
92 int board_early_init_f(void)
93 {
94 	setup_iomux_uart();
95 
96 	return 0;
97 }
98 
99 int board_usb_phy_mode(int port)
100 {
101 	return USB_INIT_DEVICE;
102 }
103 
104 int board_init(void)
105 {
106 	/* Address of boot parameters */
107 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
108 
109 	setup_usb();
110 
111 	return 0;
112 }
113 
114 int checkboard(void)
115 {
116 	puts("Board: PICO-IMX6UL-EMMC\n");
117 
118 	return 0;
119 }
120