1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015 Technexion Ltd. 4 * 5 * Author: Richard Hu <richard.hu@technexion.com> 6 */ 7 8 #include <asm/arch/clock.h> 9 #include <asm/arch/iomux.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/gpio.h> 15 #include <asm/mach-imx/iomux-v3.h> 16 #include <asm/mach-imx/mxc_i2c.h> 17 #include <asm/io.h> 18 #include <common.h> 19 #include <miiphy.h> 20 #include <netdev.h> 21 #include <i2c.h> 22 #include <linux/sizes.h> 23 #include <usb.h> 24 #include <power/pmic.h> 25 #include <power/pfuze3000_pmic.h> 26 #include "../../freescale/common/pfuze.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 32 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 33 34 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 36 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 37 PAD_CTL_ODE) 38 39 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 40 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 42 43 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 44 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) 45 46 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 47 PAD_CTL_SPEED_HIGH | \ 48 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 49 50 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 51 52 #define RMII_PHY_RESET IMX_GPIO_NR(1, 28) 53 54 #ifdef CONFIG_SYS_I2C_MXC 55 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 56 /* I2C2 for PMIC */ 57 struct i2c_pads_info i2c_pad_info1 = { 58 .scl = { 59 .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, 60 .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, 61 .gp = IMX_GPIO_NR(1, 2), 62 }, 63 .sda = { 64 .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, 65 .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, 66 .gp = IMX_GPIO_NR(1, 3), 67 }, 68 }; 69 #endif 70 71 static iomux_v3_cfg_t const fec_pads[] = { 72 MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL), 73 MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 74 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 75 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 76 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 77 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 78 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 79 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 80 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 81 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 82 MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 83 }; 84 85 static void setup_iomux_fec(void) 86 { 87 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 88 } 89 90 int board_eth_init(bd_t *bis) 91 { 92 setup_iomux_fec(); 93 94 gpio_request(RMII_PHY_RESET, "enet_phy_reset"); 95 gpio_direction_output(RMII_PHY_RESET, 0); 96 /* 97 * According to KSZ8081MNX-RNB manual: 98 * For warm reset, the reset (RST#) pin should be asserted low for a 99 * minimum of 500μs. The strap-in pin values are read and updated 100 * at the de-assertion of reset. 101 */ 102 udelay(500); 103 104 gpio_direction_output(RMII_PHY_RESET, 1); 105 /* 106 * According to KSZ8081MNX-RNB manual: 107 * After the de-assertion of reset, wait a minimum of 100μs before 108 * starting programming on the MIIM (MDC/MDIO) interface. 109 */ 110 udelay(100); 111 112 return fecmxc_initialize(bis); 113 } 114 115 static int setup_fec(void) 116 { 117 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 118 int ret; 119 120 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 121 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); 122 123 ret = enable_fec_anatop_clock(1, ENET_50MHZ); 124 if (ret) 125 return ret; 126 127 enable_enet_clk(1); 128 129 return 0; 130 } 131 132 int board_phy_config(struct phy_device *phydev) 133 { 134 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); 135 136 if (phydev->drv->config) 137 phydev->drv->config(phydev); 138 139 return 0; 140 } 141 142 int dram_init(void) 143 { 144 gd->ram_size = imx_ddr_size(); 145 146 return 0; 147 } 148 149 static iomux_v3_cfg_t const uart6_pads[] = { 150 MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 151 MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 152 }; 153 154 #define USB_OTHERREGS_OFFSET 0x800 155 #define UCTRL_PWR_POL (1 << 9) 156 157 static iomux_v3_cfg_t const usb_otg_pad[] = { 158 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), 159 }; 160 161 static void setup_iomux_uart(void) 162 { 163 imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads)); 164 } 165 166 static void setup_usb(void) 167 { 168 imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad)); 169 } 170 171 int board_early_init_f(void) 172 { 173 setup_iomux_uart(); 174 175 return 0; 176 } 177 178 #ifdef CONFIG_POWER 179 #define I2C_PMIC 0 180 static struct pmic *pfuze; 181 int power_init_board(void) 182 { 183 int ret; 184 unsigned int reg, rev_id; 185 186 ret = power_pfuze3000_init(I2C_PMIC); 187 if (ret) 188 return ret; 189 190 pfuze = pmic_get("PFUZE3000"); 191 ret = pmic_probe(pfuze); 192 if (ret) 193 return ret; 194 195 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); 196 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); 197 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); 198 199 /* disable Low Power Mode during standby mode */ 200 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); 201 202 /* SW1B step ramp up time from 2us to 4us/25mV */ 203 pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, 0x40); 204 205 /* SW1B mode to APS/PFM */ 206 pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, 0xc); 207 208 /* SW1B standby voltage set to 0.975V */ 209 pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, 0xb); 210 211 return 0; 212 } 213 #endif 214 215 int board_usb_phy_mode(int port) 216 { 217 if (port == 1) 218 return USB_INIT_HOST; 219 else 220 return USB_INIT_DEVICE; 221 } 222 223 int board_ehci_hcd_init(int port) 224 { 225 u32 *usbnc_usb_ctrl; 226 227 if (port > 1) 228 return -EINVAL; 229 230 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 231 port * 4); 232 233 /* Set Power polarity */ 234 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 235 236 return 0; 237 } 238 239 int board_init(void) 240 { 241 /* Address of boot parameters */ 242 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 243 244 #ifdef CONFIG_SYS_I2C_MXC 245 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 246 #endif 247 248 setup_fec(); 249 setup_usb(); 250 251 return 0; 252 } 253 254 int checkboard(void) 255 { 256 puts("Board: PICO-IMX6UL-EMMC\n"); 257 258 return 0; 259 } 260