1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015 Technexion Ltd. 4 * 5 * Author: Richard Hu <richard.hu@technexion.com> 6 */ 7 8 #include <asm/arch/clock.h> 9 #include <asm/arch/iomux.h> 10 #include <asm/arch/imx-regs.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/mx6-pins.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/gpio.h> 15 #include <asm/mach-imx/iomux-v3.h> 16 #include <asm/mach-imx/mxc_i2c.h> 17 #include <asm/io.h> 18 #include <common.h> 19 #include <miiphy.h> 20 #include <netdev.h> 21 #include <fsl_esdhc.h> 22 #include <i2c.h> 23 #include <linux/sizes.h> 24 #include <usb.h> 25 #include <power/pmic.h> 26 #include <power/pfuze3000_pmic.h> 27 #include "../../freescale/common/pfuze.h" 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 33 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 34 35 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 36 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 37 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 40 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 41 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 42 PAD_CTL_ODE) 43 44 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 45 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 46 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 47 48 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 49 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) 50 51 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 52 PAD_CTL_SPEED_HIGH | \ 53 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) 54 55 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 56 57 #define RMII_PHY_RESET IMX_GPIO_NR(1, 28) 58 59 #ifdef CONFIG_SYS_I2C_MXC 60 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 61 /* I2C2 for PMIC */ 62 struct i2c_pads_info i2c_pad_info1 = { 63 .scl = { 64 .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, 65 .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, 66 .gp = IMX_GPIO_NR(1, 2), 67 }, 68 .sda = { 69 .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, 70 .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, 71 .gp = IMX_GPIO_NR(1, 3), 72 }, 73 }; 74 #endif 75 76 static iomux_v3_cfg_t const fec_pads[] = { 77 MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL), 78 MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), 79 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 80 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 81 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), 82 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 83 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 84 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 85 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 86 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), 87 MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 88 }; 89 90 static void setup_iomux_fec(void) 91 { 92 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 93 } 94 95 int board_eth_init(bd_t *bis) 96 { 97 setup_iomux_fec(); 98 99 gpio_direction_output(RMII_PHY_RESET, 0); 100 /* 101 * According to KSZ8081MNX-RNB manual: 102 * For warm reset, the reset (RST#) pin should be asserted low for a 103 * minimum of 500μs. The strap-in pin values are read and updated 104 * at the de-assertion of reset. 105 */ 106 udelay(500); 107 108 gpio_direction_output(RMII_PHY_RESET, 1); 109 /* 110 * According to KSZ8081MNX-RNB manual: 111 * After the de-assertion of reset, wait a minimum of 100μs before 112 * starting programming on the MIIM (MDC/MDIO) interface. 113 */ 114 udelay(100); 115 116 return fecmxc_initialize(bis); 117 } 118 119 static int setup_fec(void) 120 { 121 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 122 int ret; 123 124 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 125 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); 126 127 ret = enable_fec_anatop_clock(1, ENET_50MHZ); 128 if (ret) 129 return ret; 130 131 enable_enet_clk(1); 132 133 return 0; 134 } 135 136 int board_phy_config(struct phy_device *phydev) 137 { 138 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); 139 140 if (phydev->drv->config) 141 phydev->drv->config(phydev); 142 143 return 0; 144 } 145 146 int dram_init(void) 147 { 148 gd->ram_size = imx_ddr_size(); 149 150 return 0; 151 } 152 153 static iomux_v3_cfg_t const uart6_pads[] = { 154 MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 155 MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 156 }; 157 158 static iomux_v3_cfg_t const usdhc1_pads[] = { 159 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 160 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 161 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 162 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 163 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 164 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 165 MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 166 MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 167 MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 168 MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 169 }; 170 171 #define USB_OTHERREGS_OFFSET 0x800 172 #define UCTRL_PWR_POL (1 << 9) 173 174 static iomux_v3_cfg_t const usb_otg_pad[] = { 175 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), 176 }; 177 178 static void setup_iomux_uart(void) 179 { 180 imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads)); 181 } 182 183 static void setup_usb(void) 184 { 185 imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad)); 186 } 187 188 static struct fsl_esdhc_cfg usdhc_cfg[1] = { 189 {USDHC1_BASE_ADDR}, 190 }; 191 192 int board_mmc_getcd(struct mmc *mmc) 193 { 194 return 1; 195 } 196 197 int board_mmc_init(bd_t *bis) 198 { 199 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 200 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 201 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 202 } 203 204 int board_early_init_f(void) 205 { 206 setup_iomux_uart(); 207 208 return 0; 209 } 210 211 #ifdef CONFIG_POWER 212 #define I2C_PMIC 0 213 static struct pmic *pfuze; 214 int power_init_board(void) 215 { 216 int ret; 217 unsigned int reg, rev_id; 218 219 ret = power_pfuze3000_init(I2C_PMIC); 220 if (ret) 221 return ret; 222 223 pfuze = pmic_get("PFUZE3000"); 224 ret = pmic_probe(pfuze); 225 if (ret) 226 return ret; 227 228 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); 229 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); 230 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); 231 232 /* disable Low Power Mode during standby mode */ 233 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); 234 235 /* SW1B step ramp up time from 2us to 4us/25mV */ 236 pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, 0x40); 237 238 /* SW1B mode to APS/PFM */ 239 pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, 0xc); 240 241 /* SW1B standby voltage set to 0.975V */ 242 pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, 0xb); 243 244 return 0; 245 } 246 #endif 247 248 int board_usb_phy_mode(int port) 249 { 250 if (port == 1) 251 return USB_INIT_HOST; 252 else 253 return USB_INIT_DEVICE; 254 } 255 256 int board_ehci_hcd_init(int port) 257 { 258 u32 *usbnc_usb_ctrl; 259 260 if (port > 1) 261 return -EINVAL; 262 263 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + 264 port * 4); 265 266 /* Set Power polarity */ 267 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); 268 269 return 0; 270 } 271 272 int board_init(void) 273 { 274 /* Address of boot parameters */ 275 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 276 277 #ifdef CONFIG_SYS_I2C_MXC 278 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 279 #endif 280 281 setup_fec(); 282 setup_usb(); 283 284 return 0; 285 } 286 287 int checkboard(void) 288 { 289 puts("Board: PICO-IMX6UL-EMMC\n"); 290 291 return 0; 292 } 293