xref: /openbmc/u-boot/board/technexion/pico-imx6ul/pico-imx6ul.c (revision 737d8bd82058e602df9c0898aeb7bddeece371dd)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2015 Technexion Ltd.
4  *
5  * Author: Richard Hu <richard.hu@technexion.com>
6  */
7 
8 #include <asm/arch/clock.h>
9 #include <asm/arch/iomux.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/gpio.h>
15 #include <asm/mach-imx/iomux-v3.h>
16 #include <asm/mach-imx/mxc_i2c.h>
17 #include <asm/io.h>
18 #include <common.h>
19 #include <miiphy.h>
20 #include <netdev.h>
21 #include <i2c.h>
22 #include <linux/sizes.h>
23 #include <usb.h>
24 #include <power/pmic.h>
25 #include <power/pfuze3000_pmic.h>
26 #include "../../freescale/common/pfuze.h"
27 
28 DECLARE_GLOBAL_DATA_PTR;
29 
30 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
31 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
32 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
33 
34 #define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
35 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
36 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
37 	PAD_CTL_ODE)
38 
39 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
40 	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
41 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
42 
43 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
44 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
45 
46 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
47 	PAD_CTL_SPEED_HIGH   |                                   \
48 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
49 
50 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
51 
52 #define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
53 
54 #ifdef CONFIG_SYS_I2C_MXC
55 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
56 /* I2C2 for PMIC */
57 struct i2c_pads_info i2c_pad_info1 = {
58 	.scl = {
59 		.i2c_mode =  MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
60 		.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
61 		.gp = IMX_GPIO_NR(1, 2),
62 	},
63 	.sda = {
64 		.i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
65 		.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
66 		.gp = IMX_GPIO_NR(1, 3),
67 	},
68 };
69 #endif
70 
71 static iomux_v3_cfg_t const fec_pads[] = {
72 	MX6_PAD_ENET1_TX_EN__ENET2_MDC		| MUX_PAD_CTRL(MDIO_PAD_CTRL),
73 	MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO	| MUX_PAD_CTRL(MDIO_PAD_CTRL),
74 	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00	| MUX_PAD_CTRL(ENET_PAD_CTRL),
75 	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01	| MUX_PAD_CTRL(ENET_PAD_CTRL),
76 	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	| MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
77 	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL),
78 	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00	| MUX_PAD_CTRL(ENET_PAD_CTRL),
79 	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01	| MUX_PAD_CTRL(ENET_PAD_CTRL),
80 	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL),
81 	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER	| MUX_PAD_CTRL(ENET_PAD_CTRL),
82 	MX6_PAD_UART4_TX_DATA__GPIO1_IO28	| MUX_PAD_CTRL(NO_PAD_CTRL),
83 };
84 
85 static void setup_iomux_fec(void)
86 {
87 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
88 }
89 
90 int board_eth_init(bd_t *bis)
91 {
92 	setup_iomux_fec();
93 
94 	gpio_direction_output(RMII_PHY_RESET, 0);
95 	/*
96 	 * According to KSZ8081MNX-RNB manual:
97 	 * For warm reset, the reset (RST#) pin should be asserted low for a
98 	 * minimum of 500μs.  The strap-in pin values are read and updated
99 	 * at the de-assertion of reset.
100 	 */
101 	udelay(500);
102 
103 	gpio_direction_output(RMII_PHY_RESET, 1);
104 	/*
105 	 * According to KSZ8081MNX-RNB manual:
106 	 * After the de-assertion of reset, wait a minimum of 100μs before
107 	 * starting programming on the MIIM (MDC/MDIO) interface.
108 	 */
109 	udelay(100);
110 
111 	return fecmxc_initialize(bis);
112 }
113 
114 static int setup_fec(void)
115 {
116 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
117 	int ret;
118 
119 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
120 			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
121 
122 	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
123 	if (ret)
124 		return ret;
125 
126 	enable_enet_clk(1);
127 
128 	return 0;
129 }
130 
131 int board_phy_config(struct phy_device *phydev)
132 {
133 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
134 
135 	if (phydev->drv->config)
136 		phydev->drv->config(phydev);
137 
138 	return 0;
139 }
140 
141 int dram_init(void)
142 {
143 	gd->ram_size = imx_ddr_size();
144 
145 	return 0;
146 }
147 
148 static iomux_v3_cfg_t const uart6_pads[] = {
149 	MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
150 	MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
151 };
152 
153 #define USB_OTHERREGS_OFFSET	0x800
154 #define UCTRL_PWR_POL		(1 << 9)
155 
156 static iomux_v3_cfg_t const usb_otg_pad[] = {
157 	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
158 };
159 
160 static void setup_iomux_uart(void)
161 {
162 	imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
163 }
164 
165 static void setup_usb(void)
166 {
167 	imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad));
168 }
169 
170 int board_early_init_f(void)
171 {
172 	setup_iomux_uart();
173 
174 	return 0;
175 }
176 
177 #ifdef CONFIG_POWER
178 #define I2C_PMIC       0
179 static struct pmic *pfuze;
180 int power_init_board(void)
181 {
182 	int ret;
183 	unsigned int reg, rev_id;
184 
185 	ret = power_pfuze3000_init(I2C_PMIC);
186 	if (ret)
187 		return ret;
188 
189 	pfuze = pmic_get("PFUZE3000");
190 	ret = pmic_probe(pfuze);
191 	if (ret)
192 		return ret;
193 
194 	pmic_reg_read(pfuze, PFUZE3000_DEVICEID, &reg);
195 	pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id);
196 	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
197 
198 	/* disable Low Power Mode during standby mode */
199 	pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
200 
201 	/* SW1B step ramp up time from 2us to 4us/25mV */
202 	pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, 0x40);
203 
204 	/* SW1B mode to APS/PFM */
205 	pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, 0xc);
206 
207 	/* SW1B standby voltage set to 0.975V */
208 	pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, 0xb);
209 
210 	return 0;
211 }
212 #endif
213 
214 int board_usb_phy_mode(int port)
215 {
216 	if (port == 1)
217 		return USB_INIT_HOST;
218 	else
219 		return USB_INIT_DEVICE;
220 }
221 
222 int board_ehci_hcd_init(int port)
223 {
224 	u32 *usbnc_usb_ctrl;
225 
226 	if (port > 1)
227 		return -EINVAL;
228 
229 	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
230 				 port * 4);
231 
232 	/* Set Power polarity */
233 	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
234 
235 	return 0;
236 }
237 
238 int board_init(void)
239 {
240 	/* Address of boot parameters */
241 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
242 
243 	#ifdef CONFIG_SYS_I2C_MXC
244 		setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
245 	#endif
246 
247 	setup_fec();
248 	setup_usb();
249 
250 	return 0;
251 }
252 
253 int checkboard(void)
254 {
255 	puts("Board: PICO-IMX6UL-EMMC\n");
256 
257 	return 0;
258 }
259