1/* 2 * Copyright (C) 2017 Soeren Moch <smoch@web.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#define __ASSEMBLY__ 8#include "asm/arch/crm_regs.h" 9#include "asm/arch/iomux.h" 10#include "asm/arch/mx6-ddr.h" 11 12/* image version 2 for imx6 */ 13IMAGE_VERSION 2 14BOOT_FROM sd 15 16/* set the default clock gates to save power */ 17DATA 4, CCM_CCGR0, 0x00C03F3F 18DATA 4, CCM_CCGR1, 0x0030FC03 19DATA 4, CCM_CCGR2, 0x0FFFC000 20DATA 4, CCM_CCGR3, 0x3FF00000 21DATA 4, CCM_CCGR4, 0x00FFF300 22DATA 4, CCM_CCGR5, 0x0F0000C3 23DATA 4, CCM_CCGR6, 0x000003FF 24/* set CKO1 (used as AUDIO_MCLK) to ahb_clk_root/8 = 16.5 MHz */ 25DATA 4, CCM_CCOSR, 0x000000fb 26 27/* enable AXI cache for VDOA/VPU/IPU */ 28DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF 29/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ 30DATA 4, MX6_IOMUXC_GPR6, 0x77177717 31DATA 4, MX6_IOMUXC_GPR7, 0x77177717 32 33 34/* 35 * DDR3/DDR3L settings 36 * use default 40 Ohm pad drive strength, no odt 37 * 4x256Mx16 DDR3L-1066 7-7-7 38 */ 39 40/* disable dq pullup */ 41DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 42/* disable dqs pullup */ 43DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 44DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 45DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 46DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 47DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 48DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 49DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 50DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 51/* set ddr input mode for dq signals */ 52DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 53/* set ddr input mode for dqs signals */ 54DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 55/* set pad calibration type to DDR3 */ 56DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 57/* ZQ calibration */ 58DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 59/* dqs write delay */ 60DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001f001f 61DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001f001f 62DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f001f 63DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001f001f 64/* dqs read delay */ 65DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 66DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 67DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 68DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 69DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 70DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 71DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 72DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 73/* dqs read gating control */ 74DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43000300 75DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03000300 76DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43000300 77DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03000300 78/* start delay line calibration */ 79DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 80/* tRFC=0x89+1,tXS=0x8e+1,tXP=3+1,tXPDLL=0xc+1,tFAW=0x17+1,tCL=0x4+3 */ 81DATA 4, MX6_MMDC_P0_MDCFG0, 0x898E7974 82/* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */ 83DATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 84/* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */ 85DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 86/* RTW_SAME=2,WTR_DIFF=3,WTW_DIFF=3,RTW_DIFF=2,RTR_DIFF=2 */ 87DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 88/* tXPR=0x8e+1,SDE2RST=0x10-2,RST2CKE=0x23-2 */ 89DATA 4, MX6_MMDC_P0_MDOR, 0x008E1023 90/* ODT timing */ 91DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 92/* read odt settings, 120 Ohm */ 93DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 94DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 95/* cs0, 15-bit row, 10-bit column, BL 8, 64-bit bus */ 96DATA 4, MX6_MMDC_P0_MDCTL, 0x841A0000 97/* interleaved bank access (row/bank/col), 5 cycles additional read delay */ 98DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 99/* 2GiByte RAM at cs0 */ 100DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 101/* load mode registers of external ddr chips */ 102DATA 4, MX6_MMDC_P0_MDSCR, 0x19308030 103DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 104DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 105DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 106/* externel chip ZQ calibration */ 107DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 108/* configure and start refreshes, 8 refresh commands at 32 kHz */ 109DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 110/* tCKE=2+1,tCKSRX=6,tCKSE=6, active power down after 256 cycles (setting 5) */ 111DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 112/* set automatic self refresh */ 113DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 114/* controller configuration finished */ 115DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 116