1/*
2 * Board-specific early ddr/sdram init.
3 *
4 * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
5 *
6 * SPDX-License-Identifier:	GPL-2.0+
7 */
8
9.equ	PPMCR0, 	0xfc04002d
10.equ	MSCR_SDRAMC,	0xec094060
11.equ	MISCCR2,	0xec09001a
12.equ	DDR_RCR,	0xfc0b8180
13.equ	DDR_PADCR,	0xfc0b81ac
14.equ	DDR_CR00,	0xfc0b8000
15.equ	DDR_CR06,	0xfc0b8018
16.equ	DDR_CR09,	0xfc0b8024
17.equ	DDR_CR40,	0xfc0b80a0
18.equ	DDR_CR45,	0xfc0b80b4
19.equ	DDR_CR56,	0xfc0b80e0
20
21.global sbf_dram_init
22.text
23
24sbf_dram_init:
25	/* CD46 = DDR on */
26	move.l	#PPMCR0, %a1
27	move.b	#46, (%a1)
28
29	/* stmark 2, max drive strength */
30	move.l	#MSCR_SDRAMC, %a1
31	move.b	#1, (%a1)
32
33	/*
34	 * use cpu clock, seems more realiable
35	 *
36	 * DDR2 clock is serviced from DDR controller as input clock / 2
37	 * so, if clock comes from
38	 *   vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
39	 *   cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
40	 *
41	 *     .
42	 *    / \    DDR2 can't be clocked lower than 125Mhz
43	 *   / ! \   DDR2 init must pass further i/dcache enable test
44	 *  /_____\
45	 *  WARNING
46	 */
47
48	/* cpu / 2 = 125 Mhz for 480 Mhz pll */
49	move.l	#MISCCR2, %a1
50	move.w	#0xa01d, (%a1)
51
52	/* DDR force sw reset settings */
53	move.l	#DDR_RCR, %a1
54	move.l	#0x00000000, (%a1)
55	move.l	#0x40000000, (%a1)
56
57	/*
58	 * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good,
59	 * 500/700 mV are ok
60	 */
61	move.l	#DDR_PADCR, %a1
62	move.l	#0x01030203, (%a1)	/* as freescale tower */
63
64	move.l	#DDR_CR00, %a1
65	move.l	#0x01010101, (%a1)+	/* 0x00 */
66	move.l	#0x00000101, (%a1)+	/* 0x04 */
67	move.l	#0x01010100, (%a1)+	/* 0x08 */
68	move.l	#0x01010000, (%a1)+	/* 0x0C */
69	move.l	#0x00010101, (%a1)+	/* 0x10 */
70	move.l	#DDR_CR06, %a1
71	move.l	#0x00010100, (%a1)+	/* 0x18 */
72	move.l	#0x00000001, (%a1)+	/* 0x1C */
73	move.l	#0x01000001, (%a1)+	/* 0x20 */
74	move.l	#0x00000100, (%a1)+	/* 0x24 */
75	move.l	#0x00010001, (%a1)+	/* 0x28 */
76	move.l	#0x00000200, (%a1)+	/* 0x2C */
77	move.l	#0x01000002, (%a1)+	/* 0x30 */
78	move.l	#0x00000000, (%a1)+	/* 0x34 */
79	move.l	#0x00000100, (%a1)+	/* 0x38 */
80	move.l	#0x02000100, (%a1)+	/* 0x3C */
81	move.l	#0x02000407, (%a1)+	/* 0x40 */
82	move.l	#0x02030007, (%a1)+	/* 0x44 */
83	move.l	#0x02000100, (%a1)+	/* 0x48 */
84	move.l	#0x0A030203, (%a1)+	/* 0x4C */
85	move.l	#0x00020708, (%a1)+	/* 0x50 */
86	move.l	#0x00050008, (%a1)+	/* 0x54 */
87	move.l	#0x04030002, (%a1)+	/* 0x58 */
88	move.l	#0x00000004, (%a1)+	/* 0x5C */
89	move.l	#0x020A0000, (%a1)+	/* 0x60 */
90	move.l	#0x0C00000E, (%a1)+	/* 0x64 */
91	move.l	#0x00002004, (%a1)+	/* 0x68 */
92	move.l	#0x00000000, (%a1)+	/* 0x6C */
93	move.l	#0x00100010, (%a1)+	/* 0x70 */
94	move.l	#0x00100010, (%a1)+	/* 0x74 */
95	move.l	#0x00000000, (%a1)+	/* 0x78 */
96	move.l	#0x07990000, (%a1)+	/* 0x7C */
97	move.l	#DDR_CR40, %a1
98	move.l	#0x00000000, (%a1)+	/* 0xA0 */
99	move.l	#0x00C80064, (%a1)+	/* 0xA4 */
100	move.l	#0x44520002, (%a1)+	/* 0xA8 */
101	move.l	#0x00C80023, (%a1)+	/* 0xAC */
102	move.l	#DDR_CR45, %a1
103	move.l	#0x0000C350, (%a1)	/* 0xB4 */
104	move.l	#DDR_CR56, %a1
105	move.l	#0x04000000, (%a1)+	/* 0xE0 */
106	move.l	#0x03000304, (%a1)+	/* 0xE4 */
107	move.l	#0x40040000, (%a1)+	/* 0xE8 */
108	move.l	#0xC0004004, (%a1)+	/* 0xEC */
109	move.l	#0x0642C000, (%a1)+	/* 0xF0 */
110	move.l	#0x00000642, (%a1)+	/* 0xF4 */
111	move.l	#DDR_CR09, %a1
112	tpf
113	move.l	#0x01000100, (%a1)	/* 0x24 */
114
115	move.l	#0x2000, %d1
116	bsr	asm_delay
117
118
119	rts
120