1 /* 2 * Board functions for Sysam AMCORE (MCF5307 based) board 3 * 4 * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 * 8 * This file copies memory testdram() from sandburst/common/sb_common.c 9 */ 10 11 #include <common.h> 12 #include <asm/immap.h> 13 #include <asm/io.h> 14 15 void init_lcd(void) 16 { 17 /* setup for possible K0108 lcd connected on the parallel port */ 18 sim_t *sim = (sim_t *)(MMAP_SIM); 19 20 out_be16(&sim->par, 0x300); 21 22 gpio_t *gpio = (gpio_t *)(MMAP_GPIO); 23 24 out_be16(&gpio->paddr, 0xfcff); 25 out_be16(&gpio->padat, 0x0c00); 26 } 27 28 int checkboard(void) 29 { 30 puts("Board: "); 31 puts("AMCORE v.001(alpha)\n"); 32 33 init_lcd(); 34 35 return 0; 36 } 37 38 /* 39 * in initdram we are here executing from flash 40 * case 1: 41 * is with no ACR/flash cache enabled 42 * nop = 40ns (scope measured) 43 */ 44 void fudelay(int usec) 45 { 46 while (usec--) 47 asm volatile ("nop"); 48 } 49 50 phys_size_t initdram(int board_type) 51 { 52 u32 dramsize, RC; 53 54 sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC); 55 56 /* 57 * SDRAM MT48LC4M32B2 details 58 * Memory block 0: 16 MB of SDRAM at address $00000000 59 * Port size: 32-bit port 60 * 61 * Memory block 0 wired as follows: 62 * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 63 * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 64 * 65 * Ensure that there is a delay of at least 100 microseconds from 66 * processor reset to the following code so that the SDRAM is ready 67 * for commands. 68 */ 69 fudelay(100); 70 71 /* 72 * DCR 73 * set proper RC as per specification 74 */ 75 RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1; 76 RC = (RC * 15) >> 4; 77 78 /* 0x8000 is the faster option */ 79 out_be16(&dc->dcr, 0x8200 | RC); 80 81 /* 82 * DACR0, page mode continuous, CMD on A20 0x0300 83 */ 84 out_be32(&dc->dacr0, 0x00003304); 85 86 dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000; 87 out_be32(&dc->dmr0, dramsize|1); 88 89 /* issue a PRECHARGE ALL */ 90 out_be32(&dc->dacr0, 0x0000330c); 91 out_be32((u32 *)0x00000004, 0xbeaddeed); 92 /* issue AUTOREFRESH */ 93 out_be32(&dc->dacr0, 0x0000b304); 94 /* let refresh occour */ 95 fudelay(1); 96 97 out_be32(&dc->dacr0, 0x0000b344); 98 out_be32((u32 *)0x00000c00, 0xbeaddeed); 99 100 return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); 101 } 102