1 /* 2 * Copyright (C) 2017 Synopsys, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dwmmc.h> 9 #include <malloc.h> 10 11 DECLARE_GLOBAL_DATA_PTR; 12 13 #define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000) 14 #define CREG_PAE (CREG_BASE + 0x180) 15 #define CREG_PAE_UPDATE (CREG_BASE + 0x194) 16 #define CREG_CPU_START (CREG_BASE + 0x400) 17 18 int board_early_init_f(void) 19 { 20 /* In current chip PAE support for DMA is broken, disabling it. */ 21 writel(0, (void __iomem *) CREG_PAE); 22 23 /* Really apply settings made above */ 24 writel(1, (void __iomem *) CREG_PAE_UPDATE); 25 26 return 0; 27 } 28 29 int board_mmc_init(bd_t *bis) 30 { 31 struct dwmci_host *host = NULL; 32 33 host = malloc(sizeof(struct dwmci_host)); 34 if (!host) { 35 printf("dwmci_host malloc fail!\n"); 36 return 1; 37 } 38 39 memset(host, 0, sizeof(struct dwmci_host)); 40 host->name = "Synopsys Mobile storage"; 41 host->ioaddr = (void *)ARC_DWMMC_BASE; 42 host->buswidth = 4; 43 host->dev_index = 0; 44 host->bus_hz = 100000000; 45 46 add_dwmci(host, host->bus_hz / 2, 400000); 47 48 return 0; 49 } 50 51 #define RESET_VECTOR_ADDR 0x0 52 53 void smp_set_core_boot_addr(unsigned long addr, int corenr) 54 { 55 /* All cores have reset vector pointing to 0 */ 56 writel(addr, (void __iomem *)RESET_VECTOR_ADDR); 57 58 /* Make sure other cores see written value in memory */ 59 flush_dcache_all(); 60 } 61 62 void smp_kick_all_cpus(void) 63 { 64 #define BITS_START_CORE1 1 65 #define BITS_START_CORE2 2 66 #define BITS_START_CORE3 3 67 68 int cmd = readl((void __iomem *)CREG_CPU_START); 69 70 cmd |= (1 << BITS_START_CORE1) | 71 (1 << BITS_START_CORE2) | 72 (1 << BITS_START_CORE3); 73 writel(cmd, (void __iomem *)CREG_CPU_START); 74 } 75