1 /* 2 * Copyright (C) 2018 Synopsys, Inc. All rights reserved. 3 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __BOARD_CLK_LIB_H 9 #define __BOARD_CLK_LIB_H 10 11 #include <common.h> 12 13 enum clk_ctl_ops { 14 CLK_SET = BIT(0), /* set frequency */ 15 CLK_GET = BIT(1), /* get frequency */ 16 CLK_ON = BIT(2), /* enable clock */ 17 CLK_OFF = BIT(3), /* disable clock */ 18 CLK_PRINT = BIT(4), /* print frequency */ 19 CLK_MHZ = BIT(5) /* all values in MHZ instead of HZ */ 20 }; 21 22 /* 23 * Depending on the clk_ctl_ops enable / disable / 24 * set clock rate from 'rate' argument / read clock to 'rate' argument / 25 * print clock rate. If CLK_MHZ flag set in clk_ctl_ops 'rate' is in MHz, 26 * otherwise - in Hz. 27 * 28 * This function expects "clk-fmeas" node in device tree: 29 * / { 30 * clk-fmeas { 31 * clocks = <&cpu_pll>, <&sys_pll>; 32 * clock-names = "cpu-pll", "sys-pll"; 33 * }; 34 * }; 35 */ 36 int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl); 37 38 #endif /* __BOARD_CLK_LIB_H */ 39