1 /* 2 * Copyright (C) 2018 Synopsys, Inc. All rights reserved. 3 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <clk.h> 9 #include <dm/device.h> 10 11 #include "clk-lib.h" 12 13 #define HZ_IN_MHZ 1000000 14 #define ceil(x, y) ({ ulong __x = (x), __y = (y); (__x + __y - 1) / __y; }) 15 16 int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl) 17 { 18 int ret; 19 ulong mhz_rate, priv_rate; 20 struct clk clk; 21 22 /* Dummy fmeas device, just to be able to use standard clk_* api */ 23 struct udevice fmeas = { 24 .name = "clk-fmeas", 25 .node = ofnode_path("/clk-fmeas"), 26 }; 27 28 ret = clk_get_by_name(&fmeas, name, &clk); 29 if (ret) { 30 pr_err("clock '%s' not found, err=%d\n", name, ret); 31 return ret; 32 } 33 34 if (ctl & CLK_ON) { 35 ret = clk_enable(&clk); 36 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) 37 return ret; 38 } 39 40 if ((ctl & CLK_SET) && rate) { 41 priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate; 42 ret = clk_set_rate(&clk, priv_rate); 43 if (ret) 44 return ret; 45 } 46 47 if (ctl & CLK_OFF) { 48 ret = clk_disable(&clk); 49 if (ret) { 50 pr_err("clock '%s' can't be disabled, err=%d\n", name, ret); 51 return ret; 52 } 53 } 54 55 priv_rate = clk_get_rate(&clk); 56 57 clk_free(&clk); 58 59 mhz_rate = ceil(priv_rate, HZ_IN_MHZ); 60 61 if (ctl & CLK_MHZ) 62 priv_rate = mhz_rate; 63 64 if ((ctl & CLK_GET) && rate) 65 *rate = priv_rate; 66 67 if ((ctl & CLK_PRINT) && (ctl & CLK_MHZ)) 68 printf("HSDK: clock '%s' rate %lu MHz\n", name, priv_rate); 69 else if (ctl & CLK_PRINT) 70 printf("HSDK: clock '%s' rate %lu Hz\n", name, priv_rate); 71 else 72 debug("HSDK: clock '%s' rate %lu MHz\n", name, mhz_rate); 73 74 return 0; 75 } 76