1 #include <common.h> 2 #include <netdev.h> 3 #include <miiphy.h> 4 #include <asm/gpio.h> 5 #include <asm/io.h> 6 #include <asm/arch/clock.h> 7 #include <asm/arch/gpio.h> 8 9 int sunxi_gmac_initialize(bd_t *bis) 10 { 11 int pin; 12 struct sunxi_ccm_reg *const ccm = 13 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 14 15 /* Set up clock gating */ 16 setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); 17 18 /* Set MII clock */ 19 #ifdef CONFIG_RGMII 20 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | 21 CCM_GMAC_CTRL_GPIT_RGMII); 22 #else 23 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | 24 CCM_GMAC_CTRL_GPIT_MII); 25 #endif 26 27 /* 28 * In order for the gmac nic to work reliable on the Bananapi, we 29 * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" 30 * of the GMAC clk register to 3. 31 */ 32 #ifdef CONFIG_TARGET_BANANAPI 33 setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10); 34 #endif 35 36 /* Configure pin mux settings for GMAC */ 37 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { 38 #ifdef CONFIG_RGMII 39 /* skip unused pins in RGMII mode */ 40 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) 41 continue; 42 #endif 43 sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC); 44 sunxi_gpio_set_drv(pin, 3); 45 } 46 47 #ifdef CONFIG_RGMII 48 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII); 49 #else 50 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII); 51 #endif 52 } 53