1 #include <common.h> 2 #include <netdev.h> 3 #include <miiphy.h> 4 #include <asm/gpio.h> 5 #include <asm/io.h> 6 #include <asm/arch/clock.h> 7 #include <asm/arch/gpio.h> 8 9 int sunxi_gmac_initialize(bd_t *bis) 10 { 11 int pin; 12 struct sunxi_ccm_reg *const ccm = 13 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 14 15 /* Set up clock gating */ 16 #ifdef CONFIG_SUNXI_GEN_SUN6I 17 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); 18 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); 19 #else 20 setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); 21 #endif 22 23 /* Set MII clock */ 24 #ifdef CONFIG_RGMII 25 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | 26 CCM_GMAC_CTRL_GPIT_RGMII); 27 setbits_le32(&ccm->gmac_clk_cfg, 28 CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); 29 #else 30 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | 31 CCM_GMAC_CTRL_GPIT_MII); 32 #endif 33 34 #ifndef CONFIG_MACH_SUN6I 35 /* Configure pin mux settings for GMAC */ 36 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { 37 #ifdef CONFIG_RGMII 38 /* skip unused pins in RGMII mode */ 39 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) 40 continue; 41 #endif 42 sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC); 43 sunxi_gpio_set_drv(pin, 3); 44 } 45 #elif defined CONFIG_RGMII 46 /* Configure sun6i RGMII mode pin mux settings */ 47 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) { 48 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); 49 sunxi_gpio_set_drv(pin, 3); 50 } 51 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 52 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); 53 sunxi_gpio_set_drv(pin, 3); 54 } 55 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) { 56 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); 57 sunxi_gpio_set_drv(pin, 3); 58 } 59 for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) { 60 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); 61 sunxi_gpio_set_drv(pin, 3); 62 } 63 #elif defined CONFIG_GMII 64 /* Configure sun6i GMII mode pin mux settings */ 65 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) { 66 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); 67 sunxi_gpio_set_drv(pin, 2); 68 } 69 #else 70 /* Configure sun6i MII mode pin mux settings */ 71 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) 72 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); 73 for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++) 74 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); 75 for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++) 76 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); 77 for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++) 78 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); 79 for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++) 80 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); 81 #endif 82 83 #ifdef CONFIG_DM_ETH 84 return 0; 85 #else 86 # ifdef CONFIG_RGMII 87 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII); 88 # elif defined CONFIG_GMII 89 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII); 90 # else 91 return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII); 92 # endif 93 #endif 94 } 95