15835823dSIan Campbell #include <common.h> 25835823dSIan Campbell #include <netdev.h> 35835823dSIan Campbell #include <miiphy.h> 45835823dSIan Campbell #include <asm/gpio.h> 55835823dSIan Campbell #include <asm/io.h> 65835823dSIan Campbell #include <asm/arch/clock.h> 75835823dSIan Campbell #include <asm/arch/gpio.h> 85835823dSIan Campbell 95835823dSIan Campbell int sunxi_gmac_initialize(bd_t *bis) 105835823dSIan Campbell { 115835823dSIan Campbell int pin; 125835823dSIan Campbell struct sunxi_ccm_reg *const ccm = 135835823dSIan Campbell (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 145835823dSIan Campbell 155835823dSIan Campbell /* Set up clock gating */ 165835823dSIan Campbell setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); 175835823dSIan Campbell 185835823dSIan Campbell /* Set MII clock */ 19*ef7e723bSChen-Yu Tsai #ifdef CONFIG_RGMII 205835823dSIan Campbell setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | 215835823dSIan Campbell CCM_GMAC_CTRL_GPIT_RGMII); 22*ef7e723bSChen-Yu Tsai #else 23*ef7e723bSChen-Yu Tsai setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | 24*ef7e723bSChen-Yu Tsai CCM_GMAC_CTRL_GPIT_MII); 25*ef7e723bSChen-Yu Tsai #endif 265835823dSIan Campbell 275835823dSIan Campbell /* Configure pin mux settings for GMAC */ 285835823dSIan Campbell for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { 29*ef7e723bSChen-Yu Tsai #ifdef CONFIG_RGMII 305835823dSIan Campbell /* skip unused pins in RGMII mode */ 315835823dSIan Campbell if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) 325835823dSIan Campbell continue; 33*ef7e723bSChen-Yu Tsai #endif 345835823dSIan Campbell sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC); 355835823dSIan Campbell sunxi_gpio_set_drv(pin, 3); 365835823dSIan Campbell } 375835823dSIan Campbell 38*ef7e723bSChen-Yu Tsai #ifdef CONFIG_RGMII 395835823dSIan Campbell return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII); 40*ef7e723bSChen-Yu Tsai #else 41*ef7e723bSChen-Yu Tsai return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII); 42*ef7e723bSChen-Yu Tsai #endif 435835823dSIan Campbell } 44