18ffc487cSHans de Goede #include <common.h> 28ffc487cSHans de Goede #include <asm/arch/dram.h> 38ffc487cSHans de Goede 48ffc487cSHans de Goede static struct dram_para dram_para = { 58ffc487cSHans de Goede .clock = CONFIG_DRAM_CLK, 68ffc487cSHans de Goede .type = 3, 78ffc487cSHans de Goede .rank_num = 1, 88ffc487cSHans de Goede .density = 0, 98ffc487cSHans de Goede .io_width = 0, 108ffc487cSHans de Goede .bus_width = 0, 118ffc487cSHans de Goede .zq = CONFIG_DRAM_ZQ, 12*47e3501aSSiarhei Siamashka .odt_en = CONFIG_DRAM_ODT_EN, 138ffc487cSHans de Goede .size = 0, 14d133647aSSiarhei Siamashka #ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC 15d133647aSSiarhei Siamashka .cas = 6, 168ffc487cSHans de Goede .tpr0 = 0x30926692, 178ffc487cSHans de Goede .tpr1 = 0x1090, 188ffc487cSHans de Goede .tpr2 = 0x1a0c8, 19d133647aSSiarhei Siamashka .emr2 = 0, 20d133647aSSiarhei Siamashka #else 21d133647aSSiarhei Siamashka # include "dram_timings_sun4i.h" 22*47e3501aSSiarhei Siamashka .active_windowing = 1, 23d133647aSSiarhei Siamashka #endif 24*47e3501aSSiarhei Siamashka .tpr3 = CONFIG_DRAM_TPR3, 258ffc487cSHans de Goede .tpr4 = 0, 268ffc487cSHans de Goede .tpr5 = 0, 278ffc487cSHans de Goede .emr1 = CONFIG_DRAM_EMR1, 288ffc487cSHans de Goede .emr3 = 0, 29*47e3501aSSiarhei Siamashka .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, 308ffc487cSHans de Goede }; 318ffc487cSHans de Goede 328ffc487cSHans de Goede unsigned long sunxi_dram_init(void) 338ffc487cSHans de Goede { 348ffc487cSHans de Goede return dramc_init(&dram_para); 358ffc487cSHans de Goede } 36