1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #include <axp_pmic.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/display.h> 20 #include <asm/arch/dram.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mmc.h> 23 #include <asm/arch/spl.h> 24 #include <asm/arch/usb_phy.h> 25 #ifndef CONFIG_ARM64 26 #include <asm/armv7.h> 27 #endif 28 #include <asm/gpio.h> 29 #include <asm/io.h> 30 #include <crc.h> 31 #include <environment.h> 32 #include <linux/libfdt.h> 33 #include <nand.h> 34 #include <net.h> 35 #include <spl.h> 36 #include <sy8106a.h> 37 #include <asm/setup.h> 38 39 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 40 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 41 int soft_i2c_gpio_sda; 42 int soft_i2c_gpio_scl; 43 44 static int soft_i2c_board_init(void) 45 { 46 int ret; 47 48 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 49 if (soft_i2c_gpio_sda < 0) { 50 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 51 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 52 return soft_i2c_gpio_sda; 53 } 54 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 55 if (ret) { 56 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 57 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 58 return ret; 59 } 60 61 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 62 if (soft_i2c_gpio_scl < 0) { 63 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 64 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 65 return soft_i2c_gpio_scl; 66 } 67 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 68 if (ret) { 69 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 70 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 71 return ret; 72 } 73 74 return 0; 75 } 76 #else 77 static int soft_i2c_board_init(void) { return 0; } 78 #endif 79 80 DECLARE_GLOBAL_DATA_PTR; 81 82 void i2c_init_board(void) 83 { 84 #ifdef CONFIG_I2C0_ENABLE 85 #if defined(CONFIG_MACH_SUN4I) || \ 86 defined(CONFIG_MACH_SUN5I) || \ 87 defined(CONFIG_MACH_SUN7I) || \ 88 defined(CONFIG_MACH_SUN8I_R40) 89 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 90 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 91 clock_twi_onoff(0, 1); 92 #elif defined(CONFIG_MACH_SUN6I) 93 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 94 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 95 clock_twi_onoff(0, 1); 96 #elif defined(CONFIG_MACH_SUN8I) 97 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 98 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 99 clock_twi_onoff(0, 1); 100 #endif 101 #endif 102 103 #ifdef CONFIG_I2C1_ENABLE 104 #if defined(CONFIG_MACH_SUN4I) || \ 105 defined(CONFIG_MACH_SUN7I) || \ 106 defined(CONFIG_MACH_SUN8I_R40) 107 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 108 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 109 clock_twi_onoff(1, 1); 110 #elif defined(CONFIG_MACH_SUN5I) 111 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 112 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 113 clock_twi_onoff(1, 1); 114 #elif defined(CONFIG_MACH_SUN6I) 115 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 116 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 117 clock_twi_onoff(1, 1); 118 #elif defined(CONFIG_MACH_SUN8I) 119 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 120 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 121 clock_twi_onoff(1, 1); 122 #endif 123 #endif 124 125 #ifdef CONFIG_I2C2_ENABLE 126 #if defined(CONFIG_MACH_SUN4I) || \ 127 defined(CONFIG_MACH_SUN7I) || \ 128 defined(CONFIG_MACH_SUN8I_R40) 129 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 130 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 131 clock_twi_onoff(2, 1); 132 #elif defined(CONFIG_MACH_SUN5I) 133 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 134 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 135 clock_twi_onoff(2, 1); 136 #elif defined(CONFIG_MACH_SUN6I) 137 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 138 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 139 clock_twi_onoff(2, 1); 140 #elif defined(CONFIG_MACH_SUN8I) 141 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 142 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 143 clock_twi_onoff(2, 1); 144 #endif 145 #endif 146 147 #ifdef CONFIG_I2C3_ENABLE 148 #if defined(CONFIG_MACH_SUN6I) 149 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 150 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 151 clock_twi_onoff(3, 1); 152 #elif defined(CONFIG_MACH_SUN7I) || \ 153 defined(CONFIG_MACH_SUN8I_R40) 154 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 155 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 156 clock_twi_onoff(3, 1); 157 #endif 158 #endif 159 160 #ifdef CONFIG_I2C4_ENABLE 161 #if defined(CONFIG_MACH_SUN7I) || \ 162 defined(CONFIG_MACH_SUN8I_R40) 163 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 164 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 165 clock_twi_onoff(4, 1); 166 #endif 167 #endif 168 169 #ifdef CONFIG_R_I2C_ENABLE 170 clock_twi_onoff(5, 1); 171 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); 172 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); 173 #endif 174 } 175 176 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT) 177 enum env_location env_get_location(enum env_operation op, int prio) 178 { 179 switch (prio) { 180 case 0: 181 return ENVL_FAT; 182 183 case 1: 184 return ENVL_MMC; 185 186 default: 187 return ENVL_UNKNOWN; 188 } 189 } 190 #endif 191 192 /* add board specific code here */ 193 int board_init(void) 194 { 195 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin; 196 197 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 198 199 #ifndef CONFIG_ARM64 200 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 201 debug("id_pfr1: 0x%08x\n", id_pfr1); 202 /* Generic Timer Extension available? */ 203 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { 204 uint32_t freq; 205 206 debug("Setting CNTFRQ\n"); 207 208 /* 209 * CNTFRQ is a secure register, so we will crash if we try to 210 * write this from the non-secure world (read is OK, though). 211 * In case some bootcode has already set the correct value, 212 * we avoid the risk of writing to it. 213 */ 214 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); 215 if (freq != COUNTER_FREQUENCY) { 216 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", 217 freq, COUNTER_FREQUENCY); 218 #ifdef CONFIG_NON_SECURE 219 printf("arch timer frequency is wrong, but cannot adjust it\n"); 220 #else 221 asm volatile("mcr p15, 0, %0, c14, c0, 0" 222 : : "r"(COUNTER_FREQUENCY)); 223 #endif 224 } 225 } 226 #endif /* !CONFIG_ARM64 */ 227 228 ret = axp_gpio_init(); 229 if (ret) 230 return ret; 231 232 #ifdef CONFIG_SATAPWR 233 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR); 234 gpio_request(satapwr_pin, "satapwr"); 235 gpio_direction_output(satapwr_pin, 1); 236 /* Give attached sata device time to power-up to avoid link timeouts */ 237 mdelay(500); 238 #endif 239 #ifdef CONFIG_MACPWR 240 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR); 241 gpio_request(macpwr_pin, "macpwr"); 242 gpio_direction_output(macpwr_pin, 1); 243 #endif 244 245 #ifdef CONFIG_DM_I2C 246 /* 247 * Temporary workaround for enabling I2C clocks until proper sunxi DM 248 * clk, reset and pinctrl drivers land. 249 */ 250 i2c_init_board(); 251 #endif 252 253 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 254 return soft_i2c_board_init(); 255 } 256 257 int dram_init(void) 258 { 259 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 260 261 return 0; 262 } 263 264 #if defined(CONFIG_NAND_SUNXI) 265 static void nand_pinmux_setup(void) 266 { 267 unsigned int pin; 268 269 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) 270 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 271 272 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I 273 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) 274 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 275 #endif 276 /* sun4i / sun7i do have a PC23, but it is not used for nand, 277 * only sun7i has a PC24 */ 278 #ifdef CONFIG_MACH_SUN7I 279 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 280 #endif 281 } 282 283 static void nand_clock_setup(void) 284 { 285 struct sunxi_ccm_reg *const ccm = 286 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 287 288 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 289 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ 290 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I 291 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); 292 #endif 293 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 294 } 295 296 void board_nand_init(void) 297 { 298 nand_pinmux_setup(); 299 nand_clock_setup(); 300 #ifndef CONFIG_SPL_BUILD 301 sunxi_nand_init(); 302 #endif 303 } 304 #endif 305 306 #ifdef CONFIG_MMC 307 static void mmc_pinmux_setup(int sdc) 308 { 309 unsigned int pin; 310 __maybe_unused int pins; 311 312 switch (sdc) { 313 case 0: 314 /* SDC0: PF0-PF5 */ 315 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 316 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 317 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 318 sunxi_gpio_set_drv(pin, 2); 319 } 320 break; 321 322 case 1: 323 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 324 325 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ 326 defined(CONFIG_MACH_SUN8I_R40) 327 if (pins == SUNXI_GPIO_H) { 328 /* SDC1: PH22-PH-27 */ 329 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 330 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 331 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 332 sunxi_gpio_set_drv(pin, 2); 333 } 334 } else { 335 /* SDC1: PG0-PG5 */ 336 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 337 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 338 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 339 sunxi_gpio_set_drv(pin, 2); 340 } 341 } 342 #elif defined(CONFIG_MACH_SUN5I) 343 /* SDC1: PG3-PG8 */ 344 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 345 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 346 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 347 sunxi_gpio_set_drv(pin, 2); 348 } 349 #elif defined(CONFIG_MACH_SUN6I) 350 /* SDC1: PG0-PG5 */ 351 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 352 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 353 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 354 sunxi_gpio_set_drv(pin, 2); 355 } 356 #elif defined(CONFIG_MACH_SUN8I) 357 if (pins == SUNXI_GPIO_D) { 358 /* SDC1: PD2-PD7 */ 359 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 360 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 361 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 362 sunxi_gpio_set_drv(pin, 2); 363 } 364 } else { 365 /* SDC1: PG0-PG5 */ 366 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 367 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 368 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 369 sunxi_gpio_set_drv(pin, 2); 370 } 371 } 372 #endif 373 break; 374 375 case 2: 376 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 377 378 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 379 /* SDC2: PC6-PC11 */ 380 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 381 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 382 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 383 sunxi_gpio_set_drv(pin, 2); 384 } 385 #elif defined(CONFIG_MACH_SUN5I) 386 if (pins == SUNXI_GPIO_E) { 387 /* SDC2: PE4-PE9 */ 388 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 389 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 390 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 391 sunxi_gpio_set_drv(pin, 2); 392 } 393 } else { 394 /* SDC2: PC6-PC15 */ 395 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 396 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 397 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 398 sunxi_gpio_set_drv(pin, 2); 399 } 400 } 401 #elif defined(CONFIG_MACH_SUN6I) 402 if (pins == SUNXI_GPIO_A) { 403 /* SDC2: PA9-PA14 */ 404 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 405 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 406 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 407 sunxi_gpio_set_drv(pin, 2); 408 } 409 } else { 410 /* SDC2: PC6-PC15, PC24 */ 411 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 412 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 413 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 414 sunxi_gpio_set_drv(pin, 2); 415 } 416 417 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 418 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 419 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 420 } 421 #elif defined(CONFIG_MACH_SUN8I_R40) 422 /* SDC2: PC6-PC15, PC24 */ 423 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 424 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 425 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 426 sunxi_gpio_set_drv(pin, 2); 427 } 428 429 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 430 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 431 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 432 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) 433 /* SDC2: PC5-PC6, PC8-PC16 */ 434 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 435 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 436 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 437 sunxi_gpio_set_drv(pin, 2); 438 } 439 440 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 441 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 442 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 443 sunxi_gpio_set_drv(pin, 2); 444 } 445 #elif defined(CONFIG_MACH_SUN9I) 446 /* SDC2: PC6-PC16 */ 447 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) { 448 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 449 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 450 sunxi_gpio_set_drv(pin, 2); 451 } 452 #endif 453 break; 454 455 case 3: 456 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 457 458 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ 459 defined(CONFIG_MACH_SUN8I_R40) 460 /* SDC3: PI4-PI9 */ 461 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 462 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 463 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 464 sunxi_gpio_set_drv(pin, 2); 465 } 466 #elif defined(CONFIG_MACH_SUN6I) 467 if (pins == SUNXI_GPIO_A) { 468 /* SDC3: PA9-PA14 */ 469 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 470 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 471 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 472 sunxi_gpio_set_drv(pin, 2); 473 } 474 } else { 475 /* SDC3: PC6-PC15, PC24 */ 476 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 477 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 478 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 479 sunxi_gpio_set_drv(pin, 2); 480 } 481 482 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 483 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 484 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 485 } 486 #endif 487 break; 488 489 default: 490 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 491 break; 492 } 493 } 494 495 int board_mmc_init(bd_t *bis) 496 { 497 __maybe_unused struct mmc *mmc0, *mmc1; 498 __maybe_unused char buf[512]; 499 500 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 501 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 502 if (!mmc0) 503 return -1; 504 505 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 506 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 507 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 508 if (!mmc1) 509 return -1; 510 #endif 511 512 return 0; 513 } 514 #endif 515 516 #ifdef CONFIG_SPL_BUILD 517 void sunxi_board_init(void) 518 { 519 int power_failed = 0; 520 521 #ifdef CONFIG_SY8106A_POWER 522 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); 523 #endif 524 525 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 526 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 527 defined CONFIG_AXP818_POWER 528 power_failed = axp_init(); 529 530 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 531 defined CONFIG_AXP818_POWER 532 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); 533 #endif 534 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); 535 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); 536 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) 537 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); 538 #endif 539 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 540 defined CONFIG_AXP818_POWER 541 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); 542 #endif 543 544 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 545 defined CONFIG_AXP818_POWER 546 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); 547 #endif 548 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); 549 #if !defined(CONFIG_AXP152_POWER) 550 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); 551 #endif 552 #ifdef CONFIG_AXP209_POWER 553 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); 554 #endif 555 556 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ 557 defined(CONFIG_AXP818_POWER) 558 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); 559 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); 560 #if !defined CONFIG_AXP809_POWER 561 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); 562 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); 563 #endif 564 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); 565 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); 566 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); 567 #endif 568 569 #ifdef CONFIG_AXP818_POWER 570 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); 571 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); 572 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); 573 #endif 574 575 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 576 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); 577 #endif 578 #endif 579 printf("DRAM:"); 580 gd->ram_size = sunxi_dram_init(); 581 printf(" %d MiB\n", (int)(gd->ram_size >> 20)); 582 if (!gd->ram_size) 583 hang(); 584 585 /* 586 * Only clock up the CPU to full speed if we are reasonably 587 * assured it's being powered with suitable core voltage 588 */ 589 if (!power_failed) 590 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 591 else 592 printf("Failed to set core voltage! Can't set CPU frequency\n"); 593 } 594 #endif 595 596 #ifdef CONFIG_USB_GADGET 597 int g_dnl_board_usb_cable_connected(void) 598 { 599 return sunxi_usb_phy_vbus_detect(0); 600 } 601 #endif 602 603 #ifdef CONFIG_SERIAL_TAG 604 void get_board_serial(struct tag_serialnr *serialnr) 605 { 606 char *serial_string; 607 unsigned long long serial; 608 609 serial_string = env_get("serial#"); 610 611 if (serial_string) { 612 serial = simple_strtoull(serial_string, NULL, 16); 613 614 serialnr->high = (unsigned int) (serial >> 32); 615 serialnr->low = (unsigned int) (serial & 0xffffffff); 616 } else { 617 serialnr->high = 0; 618 serialnr->low = 0; 619 } 620 } 621 #endif 622 623 /* 624 * Check the SPL header for the "sunxi" variant. If found: parse values 625 * that might have been passed by the loader ("fel" utility), and update 626 * the environment accordingly. 627 */ 628 static void parse_spl_header(const uint32_t spl_addr) 629 { 630 struct boot_file_head *spl = (void *)(ulong)spl_addr; 631 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0) 632 return; /* signature mismatch, no usable header */ 633 634 uint8_t spl_header_version = spl->spl_signature[3]; 635 if (spl_header_version != SPL_HEADER_VERSION) { 636 printf("sunxi SPL version mismatch: expected %u, got %u\n", 637 SPL_HEADER_VERSION, spl_header_version); 638 return; 639 } 640 if (!spl->fel_script_address) 641 return; 642 643 if (spl->fel_uEnv_length != 0) { 644 /* 645 * data is expected in uEnv.txt compatible format, so "env 646 * import -t" the string(s) at fel_script_address right away. 647 */ 648 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address, 649 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL); 650 return; 651 } 652 /* otherwise assume .scr format (mkimage-type script) */ 653 env_set_hex("fel_scriptaddr", spl->fel_script_address); 654 } 655 656 /* 657 * Note this function gets called multiple times. 658 * It must not make any changes to env variables which already exist. 659 */ 660 static void setup_environment(const void *fdt) 661 { 662 char serial_string[17] = { 0 }; 663 unsigned int sid[4]; 664 uint8_t mac_addr[6]; 665 char ethaddr[16]; 666 int i, ret; 667 668 ret = sunxi_get_sid(sid); 669 if (ret == 0 && sid[0] != 0) { 670 /* 671 * The single words 1 - 3 of the SID have quite a few bits 672 * which are the same on many models, so we take a crc32 673 * of all 3 words, to get a more unique value. 674 * 675 * Note we only do this on newer SoCs as we cannot change 676 * the algorithm on older SoCs since those have been using 677 * fixed mac-addresses based on only using word 3 for a 678 * long time and changing a fixed mac-address with an 679 * u-boot update is not good. 680 */ 681 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ 682 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ 683 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) 684 sid[3] = crc32(0, (unsigned char *)&sid[1], 12); 685 #endif 686 687 /* Ensure the NIC specific bytes of the mac are not all 0 */ 688 if ((sid[3] & 0xffffff) == 0) 689 sid[3] |= 0x800000; 690 691 for (i = 0; i < 4; i++) { 692 sprintf(ethaddr, "ethernet%d", i); 693 if (!fdt_get_alias(fdt, ethaddr)) 694 continue; 695 696 if (i == 0) 697 strcpy(ethaddr, "ethaddr"); 698 else 699 sprintf(ethaddr, "eth%daddr", i); 700 701 if (env_get(ethaddr)) 702 continue; 703 704 /* Non OUI / registered MAC address */ 705 mac_addr[0] = (i << 4) | 0x02; 706 mac_addr[1] = (sid[0] >> 0) & 0xff; 707 mac_addr[2] = (sid[3] >> 24) & 0xff; 708 mac_addr[3] = (sid[3] >> 16) & 0xff; 709 mac_addr[4] = (sid[3] >> 8) & 0xff; 710 mac_addr[5] = (sid[3] >> 0) & 0xff; 711 712 eth_env_set_enetaddr(ethaddr, mac_addr); 713 } 714 715 if (!env_get("serial#")) { 716 snprintf(serial_string, sizeof(serial_string), 717 "%08x%08x", sid[0], sid[3]); 718 719 env_set("serial#", serial_string); 720 } 721 } 722 } 723 724 int misc_init_r(void) 725 { 726 __maybe_unused int ret; 727 uint boot; 728 729 env_set("fel_booted", NULL); 730 env_set("fel_scriptaddr", NULL); 731 env_set("mmc_bootdev", NULL); 732 733 boot = sunxi_get_boot_device(); 734 /* determine if we are running in FEL mode */ 735 if (boot == BOOT_DEVICE_BOARD) { 736 env_set("fel_booted", "1"); 737 parse_spl_header(SPL_ADDR); 738 /* or if we booted from MMC, and which one */ 739 } else if (boot == BOOT_DEVICE_MMC1) { 740 env_set("mmc_bootdev", "0"); 741 } else if (boot == BOOT_DEVICE_MMC2) { 742 env_set("mmc_bootdev", "1"); 743 } 744 745 setup_environment(gd->fdt_blob); 746 747 #ifndef CONFIG_MACH_SUN9I 748 ret = sunxi_usb_phy_probe(); 749 if (ret) 750 return ret; 751 #endif 752 753 #ifdef CONFIG_USB_ETHER 754 usb_ether_init(); 755 #endif 756 757 return 0; 758 } 759 760 int ft_board_setup(void *blob, bd_t *bd) 761 { 762 int __maybe_unused r; 763 764 /* 765 * Call setup_environment again in case the boot fdt has 766 * ethernet aliases the u-boot copy does not have. 767 */ 768 setup_environment(blob); 769 770 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 771 r = sunxi_simplefb_setup(blob); 772 if (r) 773 return r; 774 #endif 775 return 0; 776 } 777 778 #ifdef CONFIG_SPL_LOAD_FIT 779 int board_fit_config_name_match(const char *name) 780 { 781 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR; 782 const char *cmp_str = (void *)(ulong)SPL_ADDR; 783 784 /* Check if there is a DT name stored in the SPL header and use that. */ 785 if (spl->dt_name_offset) { 786 cmp_str += spl->dt_name_offset; 787 } else { 788 #ifdef CONFIG_DEFAULT_DEVICE_TREE 789 cmp_str = CONFIG_DEFAULT_DEVICE_TREE; 790 #else 791 return 0; 792 #endif 793 }; 794 795 /* Differentiate the two Pine64 board DTs by their DRAM size. */ 796 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) { 797 if ((gd->ram_size > 512 * 1024 * 1024)) 798 return !strstr(name, "plus"); 799 else 800 return !!strstr(name, "plus"); 801 } else { 802 return strcmp(name, cmp_str); 803 } 804 } 805 #endif 806