1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #ifdef CONFIG_AXP152_POWER 17 #include <axp152.h> 18 #endif 19 #ifdef CONFIG_AXP209_POWER 20 #include <axp209.h> 21 #endif 22 #include <asm/arch/clock.h> 23 #include <asm/arch/cpu.h> 24 #include <asm/arch/dram.h> 25 #include <asm/arch/gpio.h> 26 #include <asm/arch/mmc.h> 27 #include <asm/io.h> 28 #include <net.h> 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 /* add board specific code here */ 33 int board_init(void) 34 { 35 int id_pfr1; 36 37 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 38 39 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 40 debug("id_pfr1: 0x%08x\n", id_pfr1); 41 /* Generic Timer Extension available? */ 42 if ((id_pfr1 >> 16) & 0xf) { 43 debug("Setting CNTFRQ\n"); 44 /* CNTFRQ == 24 MHz */ 45 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); 46 } 47 48 return 0; 49 } 50 51 int dram_init(void) 52 { 53 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 54 55 return 0; 56 } 57 58 #ifdef CONFIG_GENERIC_MMC 59 static void mmc_pinmux_setup(int sdc) 60 { 61 unsigned int pin; 62 63 switch (sdc) { 64 case 0: 65 /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */ 66 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 67 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0); 68 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 69 sunxi_gpio_set_drv(pin, 2); 70 } 71 break; 72 73 case 1: 74 /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */ 75 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 76 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1); 77 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 78 sunxi_gpio_set_drv(pin, 2); 79 } 80 break; 81 82 case 2: 83 /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */ 84 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 85 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2); 86 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 87 sunxi_gpio_set_drv(pin, 2); 88 } 89 break; 90 91 case 3: 92 /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */ 93 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 94 sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3); 95 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 96 sunxi_gpio_set_drv(pin, 2); 97 } 98 break; 99 100 default: 101 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 102 break; 103 } 104 } 105 106 int board_mmc_init(bd_t *bis) 107 { 108 __maybe_unused struct mmc *mmc0, *mmc1; 109 __maybe_unused char buf[512]; 110 111 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 112 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 113 if (!mmc0) 114 return -1; 115 116 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 117 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 118 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 119 if (!mmc1) 120 return -1; 121 #endif 122 123 #if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 124 /* 125 * Both mmc0 and mmc2 are bootable, figure out where we're booting 126 * from. Try mmc0 first, just like the brom does. 127 */ 128 if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 && 129 mmc0->block_dev.block_read(0, 16, 1, buf) == 1) { 130 buf[12] = 0; 131 if (strcmp(&buf[4], "eGON.BT0") == 0) 132 return 0; 133 } 134 135 /* no bootable card in mmc0, so we must be booting from mmc2, swap */ 136 mmc0->block_dev.dev = 1; 137 mmc1->block_dev.dev = 0; 138 #endif 139 140 return 0; 141 } 142 #endif 143 144 void i2c_init_board(void) 145 { 146 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0); 147 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0); 148 clock_twi_onoff(0, 1); 149 } 150 151 #ifdef CONFIG_SPL_BUILD 152 void sunxi_board_init(void) 153 { 154 int power_failed = 0; 155 unsigned long ramsize; 156 157 #ifdef CONFIG_AXP152_POWER 158 power_failed = axp152_init(); 159 power_failed |= axp152_set_dcdc2(1400); 160 power_failed |= axp152_set_dcdc3(1500); 161 power_failed |= axp152_set_dcdc4(1250); 162 power_failed |= axp152_set_ldo2(3000); 163 #endif 164 #ifdef CONFIG_AXP209_POWER 165 power_failed |= axp209_init(); 166 power_failed |= axp209_set_dcdc2(1400); 167 power_failed |= axp209_set_dcdc3(1250); 168 power_failed |= axp209_set_ldo2(3000); 169 power_failed |= axp209_set_ldo3(2800); 170 power_failed |= axp209_set_ldo4(2800); 171 #endif 172 173 printf("DRAM:"); 174 ramsize = sunxi_dram_init(); 175 printf(" %lu MiB\n", ramsize >> 20); 176 if (!ramsize) 177 hang(); 178 179 /* 180 * Only clock up the CPU to full speed if we are reasonably 181 * assured it's being powered with suitable core voltage 182 */ 183 if (!power_failed) 184 clock_set_pll1(CONFIG_CLK_FULL_SPEED); 185 else 186 printf("Failed to set core voltage! Can't set CPU frequency\n"); 187 } 188 #endif 189 190 #ifdef CONFIG_MISC_INIT_R 191 int misc_init_r(void) 192 { 193 if (!getenv("ethaddr")) { 194 uint32_t reg_val = readl(SUNXI_SID_BASE); 195 196 if (reg_val) { 197 uint8_t mac_addr[6]; 198 199 mac_addr[0] = 0x02; /* Non OUI / registered MAC address */ 200 mac_addr[1] = (reg_val >> 0) & 0xff; 201 reg_val = readl(SUNXI_SID_BASE + 0x0c); 202 mac_addr[2] = (reg_val >> 24) & 0xff; 203 mac_addr[3] = (reg_val >> 16) & 0xff; 204 mac_addr[4] = (reg_val >> 8) & 0xff; 205 mac_addr[5] = (reg_val >> 0) & 0xff; 206 207 eth_setenv_enetaddr("ethaddr", mac_addr); 208 } 209 } 210 211 return 0; 212 } 213 #endif 214