1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #include <axp_pmic.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/display.h> 20 #include <asm/arch/dram.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mmc.h> 23 #include <asm/arch/usb_phy.h> 24 #ifndef CONFIG_ARM64 25 #include <asm/armv7.h> 26 #endif 27 #include <asm/gpio.h> 28 #include <asm/io.h> 29 #include <nand.h> 30 #include <net.h> 31 #include <sy8106a.h> 32 33 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 34 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 35 int soft_i2c_gpio_sda; 36 int soft_i2c_gpio_scl; 37 38 static int soft_i2c_board_init(void) 39 { 40 int ret; 41 42 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 43 if (soft_i2c_gpio_sda < 0) { 44 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 45 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 46 return soft_i2c_gpio_sda; 47 } 48 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 49 if (ret) { 50 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 51 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 52 return ret; 53 } 54 55 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 56 if (soft_i2c_gpio_scl < 0) { 57 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 58 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 59 return soft_i2c_gpio_scl; 60 } 61 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 62 if (ret) { 63 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 64 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 65 return ret; 66 } 67 68 return 0; 69 } 70 #else 71 static int soft_i2c_board_init(void) { return 0; } 72 #endif 73 74 DECLARE_GLOBAL_DATA_PTR; 75 76 /* add board specific code here */ 77 int board_init(void) 78 { 79 __maybe_unused int id_pfr1, ret; 80 81 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 82 83 #ifndef CONFIG_ARM64 84 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 85 debug("id_pfr1: 0x%08x\n", id_pfr1); 86 /* Generic Timer Extension available? */ 87 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { 88 uint32_t freq; 89 90 debug("Setting CNTFRQ\n"); 91 92 /* 93 * CNTFRQ is a secure register, so we will crash if we try to 94 * write this from the non-secure world (read is OK, though). 95 * In case some bootcode has already set the correct value, 96 * we avoid the risk of writing to it. 97 */ 98 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); 99 if (freq != CONFIG_TIMER_CLK_FREQ) { 100 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", 101 freq, CONFIG_TIMER_CLK_FREQ); 102 #ifdef CONFIG_NON_SECURE 103 printf("arch timer frequency is wrong, but cannot adjust it\n"); 104 #else 105 asm volatile("mcr p15, 0, %0, c14, c0, 0" 106 : : "r"(CONFIG_TIMER_CLK_FREQ)); 107 #endif 108 } 109 } 110 #endif /* !CONFIG_ARM64 */ 111 112 ret = axp_gpio_init(); 113 if (ret) 114 return ret; 115 116 #ifdef CONFIG_SATAPWR 117 gpio_request(CONFIG_SATAPWR, "satapwr"); 118 gpio_direction_output(CONFIG_SATAPWR, 1); 119 #endif 120 #ifdef CONFIG_MACPWR 121 gpio_request(CONFIG_MACPWR, "macpwr"); 122 gpio_direction_output(CONFIG_MACPWR, 1); 123 #endif 124 125 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 126 return soft_i2c_board_init(); 127 } 128 129 int dram_init(void) 130 { 131 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 132 133 return 0; 134 } 135 136 #ifdef CONFIG_MACH_SUN50I 137 void dram_init_banksize(void) 138 { 139 /* We need to reserve the first 16MB of RAM for ATF */ 140 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024); 141 gd->bd->bi_dram[0].size = get_effective_memsize() - (16 * 1024 * 1024); 142 } 143 #endif 144 145 #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) 146 static void nand_pinmux_setup(void) 147 { 148 unsigned int pin; 149 150 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) 151 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 152 153 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I 154 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) 155 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 156 #endif 157 /* sun4i / sun7i do have a PC23, but it is not used for nand, 158 * only sun7i has a PC24 */ 159 #ifdef CONFIG_MACH_SUN7I 160 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 161 #endif 162 } 163 164 static void nand_clock_setup(void) 165 { 166 struct sunxi_ccm_reg *const ccm = 167 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 168 169 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 170 #ifdef CONFIG_MACH_SUN9I 171 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); 172 #else 173 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); 174 #endif 175 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 176 } 177 178 void board_nand_init(void) 179 { 180 nand_pinmux_setup(); 181 nand_clock_setup(); 182 } 183 #endif 184 185 #ifdef CONFIG_GENERIC_MMC 186 static void mmc_pinmux_setup(int sdc) 187 { 188 unsigned int pin; 189 __maybe_unused int pins; 190 191 switch (sdc) { 192 case 0: 193 /* SDC0: PF0-PF5 */ 194 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 195 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 196 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 197 sunxi_gpio_set_drv(pin, 2); 198 } 199 break; 200 201 case 1: 202 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 203 204 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 205 if (pins == SUNXI_GPIO_H) { 206 /* SDC1: PH22-PH-27 */ 207 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 208 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 209 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 210 sunxi_gpio_set_drv(pin, 2); 211 } 212 } else { 213 /* SDC1: PG0-PG5 */ 214 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 215 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 216 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 217 sunxi_gpio_set_drv(pin, 2); 218 } 219 } 220 #elif defined(CONFIG_MACH_SUN5I) 221 /* SDC1: PG3-PG8 */ 222 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 223 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 224 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 225 sunxi_gpio_set_drv(pin, 2); 226 } 227 #elif defined(CONFIG_MACH_SUN6I) 228 /* SDC1: PG0-PG5 */ 229 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 230 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 231 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 232 sunxi_gpio_set_drv(pin, 2); 233 } 234 #elif defined(CONFIG_MACH_SUN8I) 235 if (pins == SUNXI_GPIO_D) { 236 /* SDC1: PD2-PD7 */ 237 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 238 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 239 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 240 sunxi_gpio_set_drv(pin, 2); 241 } 242 } else { 243 /* SDC1: PG0-PG5 */ 244 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 245 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 246 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 247 sunxi_gpio_set_drv(pin, 2); 248 } 249 } 250 #endif 251 break; 252 253 case 2: 254 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 255 256 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 257 /* SDC2: PC6-PC11 */ 258 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 259 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 260 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 261 sunxi_gpio_set_drv(pin, 2); 262 } 263 #elif defined(CONFIG_MACH_SUN5I) 264 if (pins == SUNXI_GPIO_E) { 265 /* SDC2: PE4-PE9 */ 266 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 267 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 268 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 269 sunxi_gpio_set_drv(pin, 2); 270 } 271 } else { 272 /* SDC2: PC6-PC15 */ 273 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 274 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 275 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 276 sunxi_gpio_set_drv(pin, 2); 277 } 278 } 279 #elif defined(CONFIG_MACH_SUN6I) 280 if (pins == SUNXI_GPIO_A) { 281 /* SDC2: PA9-PA14 */ 282 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 283 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 284 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 285 sunxi_gpio_set_drv(pin, 2); 286 } 287 } else { 288 /* SDC2: PC6-PC15, PC24 */ 289 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 290 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 291 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 292 sunxi_gpio_set_drv(pin, 2); 293 } 294 295 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 296 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 297 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 298 } 299 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) 300 /* SDC2: PC5-PC6, PC8-PC16 */ 301 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 302 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 303 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 304 sunxi_gpio_set_drv(pin, 2); 305 } 306 307 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 308 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 309 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 310 sunxi_gpio_set_drv(pin, 2); 311 } 312 #endif 313 break; 314 315 case 3: 316 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 317 318 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 319 /* SDC3: PI4-PI9 */ 320 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 321 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 322 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 323 sunxi_gpio_set_drv(pin, 2); 324 } 325 #elif defined(CONFIG_MACH_SUN6I) 326 if (pins == SUNXI_GPIO_A) { 327 /* SDC3: PA9-PA14 */ 328 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 329 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 330 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 331 sunxi_gpio_set_drv(pin, 2); 332 } 333 } else { 334 /* SDC3: PC6-PC15, PC24 */ 335 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 336 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 337 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 338 sunxi_gpio_set_drv(pin, 2); 339 } 340 341 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 342 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 343 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 344 } 345 #endif 346 break; 347 348 default: 349 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 350 break; 351 } 352 } 353 354 int board_mmc_init(bd_t *bis) 355 { 356 __maybe_unused struct mmc *mmc0, *mmc1; 357 __maybe_unused char buf[512]; 358 359 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 360 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 361 if (!mmc0) 362 return -1; 363 364 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 365 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 366 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 367 if (!mmc1) 368 return -1; 369 #endif 370 371 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 372 /* 373 * On systems with an emmc (mmc2), figure out if we are booting from 374 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. 375 * are searched there first. Note we only do this for u-boot proper, 376 * not for the SPL, see spl_boot_device(). 377 */ 378 if (!sunxi_mmc_has_egon_boot_signature(mmc0) && 379 sunxi_mmc_has_egon_boot_signature(mmc1)) { 380 /* Booting from emmc / mmc2, swap */ 381 mmc0->block_dev.devnum = 1; 382 mmc1->block_dev.devnum = 0; 383 } 384 #endif 385 386 return 0; 387 } 388 #endif 389 390 void i2c_init_board(void) 391 { 392 #ifdef CONFIG_I2C0_ENABLE 393 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) 394 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 395 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 396 clock_twi_onoff(0, 1); 397 #elif defined(CONFIG_MACH_SUN6I) 398 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 399 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 400 clock_twi_onoff(0, 1); 401 #elif defined(CONFIG_MACH_SUN8I) 402 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 403 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 404 clock_twi_onoff(0, 1); 405 #endif 406 #endif 407 408 #ifdef CONFIG_I2C1_ENABLE 409 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 410 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 411 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 412 clock_twi_onoff(1, 1); 413 #elif defined(CONFIG_MACH_SUN5I) 414 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 415 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 416 clock_twi_onoff(1, 1); 417 #elif defined(CONFIG_MACH_SUN6I) 418 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 419 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 420 clock_twi_onoff(1, 1); 421 #elif defined(CONFIG_MACH_SUN8I) 422 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 423 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 424 clock_twi_onoff(1, 1); 425 #endif 426 #endif 427 428 #ifdef CONFIG_I2C2_ENABLE 429 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 430 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 431 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 432 clock_twi_onoff(2, 1); 433 #elif defined(CONFIG_MACH_SUN5I) 434 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 435 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 436 clock_twi_onoff(2, 1); 437 #elif defined(CONFIG_MACH_SUN6I) 438 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 439 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 440 clock_twi_onoff(2, 1); 441 #elif defined(CONFIG_MACH_SUN8I) 442 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 443 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 444 clock_twi_onoff(2, 1); 445 #endif 446 #endif 447 448 #ifdef CONFIG_I2C3_ENABLE 449 #if defined(CONFIG_MACH_SUN6I) 450 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 451 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 452 clock_twi_onoff(3, 1); 453 #elif defined(CONFIG_MACH_SUN7I) 454 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 455 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 456 clock_twi_onoff(3, 1); 457 #endif 458 #endif 459 460 #ifdef CONFIG_I2C4_ENABLE 461 #if defined(CONFIG_MACH_SUN7I) 462 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 463 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 464 clock_twi_onoff(4, 1); 465 #endif 466 #endif 467 468 #ifdef CONFIG_R_I2C_ENABLE 469 clock_twi_onoff(5, 1); 470 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); 471 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); 472 #endif 473 } 474 475 #ifdef CONFIG_SPL_BUILD 476 void sunxi_board_init(void) 477 { 478 int power_failed = 0; 479 unsigned long ramsize; 480 481 #ifdef CONFIG_SY8106A_POWER 482 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); 483 #endif 484 485 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 486 defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER 487 power_failed = axp_init(); 488 489 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER 490 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); 491 #endif 492 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); 493 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); 494 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) 495 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); 496 #endif 497 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER 498 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); 499 #endif 500 501 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER 502 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); 503 #endif 504 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); 505 #if !defined(CONFIG_AXP152_POWER) 506 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); 507 #endif 508 #ifdef CONFIG_AXP209_POWER 509 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); 510 #endif 511 512 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER) 513 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); 514 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); 515 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); 516 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); 517 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); 518 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); 519 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); 520 #endif 521 522 #ifdef CONFIG_AXP818_POWER 523 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); 524 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); 525 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); 526 #endif 527 #endif 528 printf("DRAM:"); 529 ramsize = sunxi_dram_init(); 530 printf(" %lu MiB\n", ramsize >> 20); 531 if (!ramsize) 532 hang(); 533 534 /* 535 * Only clock up the CPU to full speed if we are reasonably 536 * assured it's being powered with suitable core voltage 537 */ 538 if (!power_failed) 539 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 540 else 541 printf("Failed to set core voltage! Can't set CPU frequency\n"); 542 } 543 #endif 544 545 #ifdef CONFIG_USB_GADGET 546 int g_dnl_board_usb_cable_connected(void) 547 { 548 return sunxi_usb_phy_vbus_detect(0); 549 } 550 #endif 551 552 #ifdef CONFIG_SERIAL_TAG 553 void get_board_serial(struct tag_serialnr *serialnr) 554 { 555 char *serial_string; 556 unsigned long long serial; 557 558 serial_string = getenv("serial#"); 559 560 if (serial_string) { 561 serial = simple_strtoull(serial_string, NULL, 16); 562 563 serialnr->high = (unsigned int) (serial >> 32); 564 serialnr->low = (unsigned int) (serial & 0xffffffff); 565 } else { 566 serialnr->high = 0; 567 serialnr->low = 0; 568 } 569 } 570 #endif 571 572 #if !defined(CONFIG_SPL_BUILD) 573 #include <asm/arch/spl.h> 574 575 /* 576 * Check the SPL header for the "sunxi" variant. If found: parse values 577 * that might have been passed by the loader ("fel" utility), and update 578 * the environment accordingly. 579 */ 580 static void parse_spl_header(const uint32_t spl_addr) 581 { 582 struct boot_file_head *spl = (void *)(ulong)spl_addr; 583 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) { 584 uint8_t spl_header_version = spl->spl_signature[3]; 585 if (spl_header_version == SPL_HEADER_VERSION) { 586 if (spl->fel_script_address) 587 setenv_hex("fel_scriptaddr", 588 spl->fel_script_address); 589 return; 590 } 591 printf("sunxi SPL version mismatch: expected %u, got %u\n", 592 SPL_HEADER_VERSION, spl_header_version); 593 } 594 } 595 #endif 596 597 #ifdef CONFIG_MISC_INIT_R 598 int misc_init_r(void) 599 { 600 char serial_string[17] = { 0 }; 601 unsigned int sid[4]; 602 uint8_t mac_addr[6]; 603 int ret; 604 605 #if !defined(CONFIG_SPL_BUILD) 606 setenv("fel_booted", NULL); 607 setenv("fel_scriptaddr", NULL); 608 /* determine if we are running in FEL mode */ 609 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ 610 setenv("fel_booted", "1"); 611 parse_spl_header(SPL_ADDR); 612 } 613 #endif 614 615 ret = sunxi_get_sid(sid); 616 if (ret == 0 && sid[0] != 0 && sid[3] != 0) { 617 if (!getenv("ethaddr")) { 618 /* Non OUI / registered MAC address */ 619 mac_addr[0] = 0x02; 620 mac_addr[1] = (sid[0] >> 0) & 0xff; 621 mac_addr[2] = (sid[3] >> 24) & 0xff; 622 mac_addr[3] = (sid[3] >> 16) & 0xff; 623 mac_addr[4] = (sid[3] >> 8) & 0xff; 624 mac_addr[5] = (sid[3] >> 0) & 0xff; 625 626 eth_setenv_enetaddr("ethaddr", mac_addr); 627 } 628 629 if (!getenv("serial#")) { 630 snprintf(serial_string, sizeof(serial_string), 631 "%08x%08x", sid[0], sid[3]); 632 633 setenv("serial#", serial_string); 634 } 635 } 636 637 #ifndef CONFIG_MACH_SUN9I 638 ret = sunxi_usb_phy_probe(); 639 if (ret) 640 return ret; 641 #endif 642 sunxi_musb_board_init(); 643 644 return 0; 645 } 646 #endif 647 648 int ft_board_setup(void *blob, bd_t *bd) 649 { 650 int __maybe_unused r; 651 652 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 653 r = sunxi_simplefb_setup(blob); 654 if (r) 655 return r; 656 #endif 657 return 0; 658 } 659