1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #include <axp_pmic.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/display.h> 20 #include <asm/arch/dram.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mmc.h> 23 #include <asm/arch/spl.h> 24 #include <asm/arch/usb_phy.h> 25 #ifndef CONFIG_ARM64 26 #include <asm/armv7.h> 27 #endif 28 #include <asm/gpio.h> 29 #include <asm/io.h> 30 #include <environment.h> 31 #include <libfdt.h> 32 #include <nand.h> 33 #include <net.h> 34 #include <sy8106a.h> 35 36 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 37 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 38 int soft_i2c_gpio_sda; 39 int soft_i2c_gpio_scl; 40 41 static int soft_i2c_board_init(void) 42 { 43 int ret; 44 45 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 46 if (soft_i2c_gpio_sda < 0) { 47 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 48 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 49 return soft_i2c_gpio_sda; 50 } 51 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 52 if (ret) { 53 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 54 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 55 return ret; 56 } 57 58 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 59 if (soft_i2c_gpio_scl < 0) { 60 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 61 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 62 return soft_i2c_gpio_scl; 63 } 64 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 65 if (ret) { 66 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 67 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 68 return ret; 69 } 70 71 return 0; 72 } 73 #else 74 static int soft_i2c_board_init(void) { return 0; } 75 #endif 76 77 DECLARE_GLOBAL_DATA_PTR; 78 79 /* add board specific code here */ 80 int board_init(void) 81 { 82 __maybe_unused int id_pfr1, ret; 83 84 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 85 86 #ifndef CONFIG_ARM64 87 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 88 debug("id_pfr1: 0x%08x\n", id_pfr1); 89 /* Generic Timer Extension available? */ 90 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { 91 uint32_t freq; 92 93 debug("Setting CNTFRQ\n"); 94 95 /* 96 * CNTFRQ is a secure register, so we will crash if we try to 97 * write this from the non-secure world (read is OK, though). 98 * In case some bootcode has already set the correct value, 99 * we avoid the risk of writing to it. 100 */ 101 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); 102 if (freq != CONFIG_TIMER_CLK_FREQ) { 103 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", 104 freq, CONFIG_TIMER_CLK_FREQ); 105 #ifdef CONFIG_NON_SECURE 106 printf("arch timer frequency is wrong, but cannot adjust it\n"); 107 #else 108 asm volatile("mcr p15, 0, %0, c14, c0, 0" 109 : : "r"(CONFIG_TIMER_CLK_FREQ)); 110 #endif 111 } 112 } 113 #endif /* !CONFIG_ARM64 */ 114 115 ret = axp_gpio_init(); 116 if (ret) 117 return ret; 118 119 #ifdef CONFIG_SATAPWR 120 gpio_request(CONFIG_SATAPWR, "satapwr"); 121 gpio_direction_output(CONFIG_SATAPWR, 1); 122 #endif 123 #ifdef CONFIG_MACPWR 124 gpio_request(CONFIG_MACPWR, "macpwr"); 125 gpio_direction_output(CONFIG_MACPWR, 1); 126 #endif 127 128 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 129 return soft_i2c_board_init(); 130 } 131 132 int dram_init(void) 133 { 134 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 135 136 return 0; 137 } 138 139 #if defined(CONFIG_NAND_SUNXI) 140 static void nand_pinmux_setup(void) 141 { 142 unsigned int pin; 143 144 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) 145 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 146 147 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I 148 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) 149 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 150 #endif 151 /* sun4i / sun7i do have a PC23, but it is not used for nand, 152 * only sun7i has a PC24 */ 153 #ifdef CONFIG_MACH_SUN7I 154 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 155 #endif 156 } 157 158 static void nand_clock_setup(void) 159 { 160 struct sunxi_ccm_reg *const ccm = 161 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 162 163 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 164 #ifdef CONFIG_MACH_SUN9I 165 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); 166 #else 167 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); 168 #endif 169 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 170 } 171 172 void board_nand_init(void) 173 { 174 nand_pinmux_setup(); 175 nand_clock_setup(); 176 #ifndef CONFIG_SPL_BUILD 177 sunxi_nand_init(); 178 #endif 179 } 180 #endif 181 182 #ifdef CONFIG_GENERIC_MMC 183 static void mmc_pinmux_setup(int sdc) 184 { 185 unsigned int pin; 186 __maybe_unused int pins; 187 188 switch (sdc) { 189 case 0: 190 /* SDC0: PF0-PF5 */ 191 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 192 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 193 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 194 sunxi_gpio_set_drv(pin, 2); 195 } 196 break; 197 198 case 1: 199 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 200 201 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 202 if (pins == SUNXI_GPIO_H) { 203 /* SDC1: PH22-PH-27 */ 204 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 205 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 206 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 207 sunxi_gpio_set_drv(pin, 2); 208 } 209 } else { 210 /* SDC1: PG0-PG5 */ 211 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 212 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 213 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 214 sunxi_gpio_set_drv(pin, 2); 215 } 216 } 217 #elif defined(CONFIG_MACH_SUN5I) 218 /* SDC1: PG3-PG8 */ 219 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 220 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 221 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 222 sunxi_gpio_set_drv(pin, 2); 223 } 224 #elif defined(CONFIG_MACH_SUN6I) 225 /* SDC1: PG0-PG5 */ 226 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 227 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 228 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 229 sunxi_gpio_set_drv(pin, 2); 230 } 231 #elif defined(CONFIG_MACH_SUN8I) 232 if (pins == SUNXI_GPIO_D) { 233 /* SDC1: PD2-PD7 */ 234 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 235 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 236 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 237 sunxi_gpio_set_drv(pin, 2); 238 } 239 } else { 240 /* SDC1: PG0-PG5 */ 241 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 242 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 243 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 244 sunxi_gpio_set_drv(pin, 2); 245 } 246 } 247 #endif 248 break; 249 250 case 2: 251 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 252 253 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 254 /* SDC2: PC6-PC11 */ 255 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 256 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 257 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 258 sunxi_gpio_set_drv(pin, 2); 259 } 260 #elif defined(CONFIG_MACH_SUN5I) 261 if (pins == SUNXI_GPIO_E) { 262 /* SDC2: PE4-PE9 */ 263 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 264 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 265 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 266 sunxi_gpio_set_drv(pin, 2); 267 } 268 } else { 269 /* SDC2: PC6-PC15 */ 270 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 271 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 272 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 273 sunxi_gpio_set_drv(pin, 2); 274 } 275 } 276 #elif defined(CONFIG_MACH_SUN6I) 277 if (pins == SUNXI_GPIO_A) { 278 /* SDC2: PA9-PA14 */ 279 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 280 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 281 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 282 sunxi_gpio_set_drv(pin, 2); 283 } 284 } else { 285 /* SDC2: PC6-PC15, PC24 */ 286 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 287 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 288 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 289 sunxi_gpio_set_drv(pin, 2); 290 } 291 292 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 293 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 294 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 295 } 296 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) 297 /* SDC2: PC5-PC6, PC8-PC16 */ 298 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 299 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 300 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 301 sunxi_gpio_set_drv(pin, 2); 302 } 303 304 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 305 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 306 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 307 sunxi_gpio_set_drv(pin, 2); 308 } 309 #endif 310 break; 311 312 case 3: 313 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 314 315 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 316 /* SDC3: PI4-PI9 */ 317 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 318 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 319 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 320 sunxi_gpio_set_drv(pin, 2); 321 } 322 #elif defined(CONFIG_MACH_SUN6I) 323 if (pins == SUNXI_GPIO_A) { 324 /* SDC3: PA9-PA14 */ 325 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 326 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 327 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 328 sunxi_gpio_set_drv(pin, 2); 329 } 330 } else { 331 /* SDC3: PC6-PC15, PC24 */ 332 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 333 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 334 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 335 sunxi_gpio_set_drv(pin, 2); 336 } 337 338 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 339 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 340 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 341 } 342 #endif 343 break; 344 345 default: 346 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 347 break; 348 } 349 } 350 351 int board_mmc_init(bd_t *bis) 352 { 353 __maybe_unused struct mmc *mmc0, *mmc1; 354 __maybe_unused char buf[512]; 355 356 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 357 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 358 if (!mmc0) 359 return -1; 360 361 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 362 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 363 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 364 if (!mmc1) 365 return -1; 366 #endif 367 368 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 369 /* 370 * On systems with an emmc (mmc2), figure out if we are booting from 371 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. 372 * are searched there first. Note we only do this for u-boot proper, 373 * not for the SPL, see spl_boot_device(). 374 */ 375 if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) { 376 /* Booting from emmc / mmc2, swap */ 377 mmc0->block_dev.devnum = 1; 378 mmc1->block_dev.devnum = 0; 379 } 380 #endif 381 382 return 0; 383 } 384 #endif 385 386 void i2c_init_board(void) 387 { 388 #ifdef CONFIG_I2C0_ENABLE 389 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) 390 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 391 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 392 clock_twi_onoff(0, 1); 393 #elif defined(CONFIG_MACH_SUN6I) 394 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 395 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 396 clock_twi_onoff(0, 1); 397 #elif defined(CONFIG_MACH_SUN8I) 398 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 399 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 400 clock_twi_onoff(0, 1); 401 #endif 402 #endif 403 404 #ifdef CONFIG_I2C1_ENABLE 405 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 406 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 407 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 408 clock_twi_onoff(1, 1); 409 #elif defined(CONFIG_MACH_SUN5I) 410 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 411 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 412 clock_twi_onoff(1, 1); 413 #elif defined(CONFIG_MACH_SUN6I) 414 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 415 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 416 clock_twi_onoff(1, 1); 417 #elif defined(CONFIG_MACH_SUN8I) 418 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 419 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 420 clock_twi_onoff(1, 1); 421 #endif 422 #endif 423 424 #ifdef CONFIG_I2C2_ENABLE 425 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 426 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 427 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 428 clock_twi_onoff(2, 1); 429 #elif defined(CONFIG_MACH_SUN5I) 430 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 431 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 432 clock_twi_onoff(2, 1); 433 #elif defined(CONFIG_MACH_SUN6I) 434 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 435 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 436 clock_twi_onoff(2, 1); 437 #elif defined(CONFIG_MACH_SUN8I) 438 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 439 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 440 clock_twi_onoff(2, 1); 441 #endif 442 #endif 443 444 #ifdef CONFIG_I2C3_ENABLE 445 #if defined(CONFIG_MACH_SUN6I) 446 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 447 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 448 clock_twi_onoff(3, 1); 449 #elif defined(CONFIG_MACH_SUN7I) 450 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 451 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 452 clock_twi_onoff(3, 1); 453 #endif 454 #endif 455 456 #ifdef CONFIG_I2C4_ENABLE 457 #if defined(CONFIG_MACH_SUN7I) 458 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 459 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 460 clock_twi_onoff(4, 1); 461 #endif 462 #endif 463 464 #ifdef CONFIG_R_I2C_ENABLE 465 clock_twi_onoff(5, 1); 466 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); 467 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); 468 #endif 469 } 470 471 #ifdef CONFIG_SPL_BUILD 472 void sunxi_board_init(void) 473 { 474 int power_failed = 0; 475 unsigned long ramsize; 476 477 #ifdef CONFIG_SY8106A_POWER 478 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); 479 #endif 480 481 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 482 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 483 defined CONFIG_AXP818_POWER 484 power_failed = axp_init(); 485 486 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 487 defined CONFIG_AXP818_POWER 488 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); 489 #endif 490 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); 491 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); 492 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) 493 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); 494 #endif 495 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 496 defined CONFIG_AXP818_POWER 497 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); 498 #endif 499 500 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 501 defined CONFIG_AXP818_POWER 502 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); 503 #endif 504 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); 505 #if !defined(CONFIG_AXP152_POWER) 506 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); 507 #endif 508 #ifdef CONFIG_AXP209_POWER 509 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); 510 #endif 511 512 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ 513 defined(CONFIG_AXP818_POWER) 514 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); 515 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); 516 #if !defined CONFIG_AXP809_POWER 517 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); 518 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); 519 #endif 520 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); 521 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); 522 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); 523 #endif 524 525 #ifdef CONFIG_AXP818_POWER 526 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); 527 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); 528 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); 529 #endif 530 531 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 532 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); 533 #endif 534 #endif 535 printf("DRAM:"); 536 ramsize = sunxi_dram_init(); 537 printf(" %d MiB\n", (int)(ramsize >> 20)); 538 if (!ramsize) 539 hang(); 540 541 /* 542 * Only clock up the CPU to full speed if we are reasonably 543 * assured it's being powered with suitable core voltage 544 */ 545 if (!power_failed) 546 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 547 else 548 printf("Failed to set core voltage! Can't set CPU frequency\n"); 549 } 550 #endif 551 552 #ifdef CONFIG_USB_GADGET 553 int g_dnl_board_usb_cable_connected(void) 554 { 555 return sunxi_usb_phy_vbus_detect(0); 556 } 557 #endif 558 559 #ifdef CONFIG_SERIAL_TAG 560 void get_board_serial(struct tag_serialnr *serialnr) 561 { 562 char *serial_string; 563 unsigned long long serial; 564 565 serial_string = getenv("serial#"); 566 567 if (serial_string) { 568 serial = simple_strtoull(serial_string, NULL, 16); 569 570 serialnr->high = (unsigned int) (serial >> 32); 571 serialnr->low = (unsigned int) (serial & 0xffffffff); 572 } else { 573 serialnr->high = 0; 574 serialnr->low = 0; 575 } 576 } 577 #endif 578 579 /* 580 * Check the SPL header for the "sunxi" variant. If found: parse values 581 * that might have been passed by the loader ("fel" utility), and update 582 * the environment accordingly. 583 */ 584 static void parse_spl_header(const uint32_t spl_addr) 585 { 586 struct boot_file_head *spl = (void *)(ulong)spl_addr; 587 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0) 588 return; /* signature mismatch, no usable header */ 589 590 uint8_t spl_header_version = spl->spl_signature[3]; 591 if (spl_header_version != SPL_HEADER_VERSION) { 592 printf("sunxi SPL version mismatch: expected %u, got %u\n", 593 SPL_HEADER_VERSION, spl_header_version); 594 return; 595 } 596 if (!spl->fel_script_address) 597 return; 598 599 if (spl->fel_uEnv_length != 0) { 600 /* 601 * data is expected in uEnv.txt compatible format, so "env 602 * import -t" the string(s) at fel_script_address right away. 603 */ 604 himport_r(&env_htab, (char *)spl->fel_script_address, 605 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL); 606 return; 607 } 608 /* otherwise assume .scr format (mkimage-type script) */ 609 setenv_hex("fel_scriptaddr", spl->fel_script_address); 610 } 611 612 /* 613 * Note this function gets called multiple times. 614 * It must not make any changes to env variables which already exist. 615 */ 616 static void setup_environment(const void *fdt) 617 { 618 char serial_string[17] = { 0 }; 619 unsigned int sid[4]; 620 uint8_t mac_addr[6]; 621 char ethaddr[16]; 622 int i, ret; 623 624 ret = sunxi_get_sid(sid); 625 if (ret == 0 && sid[0] != 0 && sid[3] != 0) { 626 for (i = 0; i < 4; i++) { 627 sprintf(ethaddr, "ethernet%d", i); 628 if (!fdt_get_alias(fdt, ethaddr)) 629 continue; 630 631 if (i == 0) 632 strcpy(ethaddr, "ethaddr"); 633 else 634 sprintf(ethaddr, "eth%daddr", i); 635 636 if (getenv(ethaddr)) 637 continue; 638 639 /* Non OUI / registered MAC address */ 640 mac_addr[0] = (i << 4) | 0x02; 641 mac_addr[1] = (sid[0] >> 0) & 0xff; 642 mac_addr[2] = (sid[3] >> 24) & 0xff; 643 mac_addr[3] = (sid[3] >> 16) & 0xff; 644 mac_addr[4] = (sid[3] >> 8) & 0xff; 645 mac_addr[5] = (sid[3] >> 0) & 0xff; 646 647 eth_setenv_enetaddr(ethaddr, mac_addr); 648 } 649 650 if (!getenv("serial#")) { 651 snprintf(serial_string, sizeof(serial_string), 652 "%08x%08x", sid[0], sid[3]); 653 654 setenv("serial#", serial_string); 655 } 656 } 657 } 658 659 int misc_init_r(void) 660 { 661 __maybe_unused int ret; 662 663 setenv("fel_booted", NULL); 664 setenv("fel_scriptaddr", NULL); 665 /* determine if we are running in FEL mode */ 666 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ 667 setenv("fel_booted", "1"); 668 parse_spl_header(SPL_ADDR); 669 } 670 671 setup_environment(gd->fdt_blob); 672 673 #ifndef CONFIG_MACH_SUN9I 674 ret = sunxi_usb_phy_probe(); 675 if (ret) 676 return ret; 677 #endif 678 sunxi_musb_board_init(); 679 680 return 0; 681 } 682 683 int ft_board_setup(void *blob, bd_t *bd) 684 { 685 int __maybe_unused r; 686 687 /* 688 * Call setup_environment again in case the boot fdt has 689 * ethernet aliases the u-boot copy does not have. 690 */ 691 setup_environment(blob); 692 693 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 694 r = sunxi_simplefb_setup(blob); 695 if (r) 696 return r; 697 #endif 698 return 0; 699 } 700