1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #ifdef CONFIG_AXP152_POWER 17 #include <axp152.h> 18 #endif 19 #ifdef CONFIG_AXP209_POWER 20 #include <axp209.h> 21 #endif 22 #ifdef CONFIG_AXP221_POWER 23 #include <axp221.h> 24 #endif 25 #include <asm/arch/clock.h> 26 #include <asm/arch/cpu.h> 27 #include <asm/arch/display.h> 28 #include <asm/arch/dram.h> 29 #include <asm/arch/gpio.h> 30 #include <asm/arch/mmc.h> 31 #include <asm/arch/usb_phy.h> 32 #include <asm/gpio.h> 33 #include <asm/io.h> 34 #include <nand.h> 35 #include <net.h> 36 37 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 38 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 39 int soft_i2c_gpio_sda; 40 int soft_i2c_gpio_scl; 41 42 static int soft_i2c_board_init(void) 43 { 44 int ret; 45 46 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 47 if (soft_i2c_gpio_sda < 0) { 48 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 49 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 50 return soft_i2c_gpio_sda; 51 } 52 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 53 if (ret) { 54 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 55 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 56 return ret; 57 } 58 59 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 60 if (soft_i2c_gpio_scl < 0) { 61 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 62 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 63 return soft_i2c_gpio_scl; 64 } 65 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 66 if (ret) { 67 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 68 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 69 return ret; 70 } 71 72 return 0; 73 } 74 #else 75 static int soft_i2c_board_init(void) { return 0; } 76 #endif 77 78 DECLARE_GLOBAL_DATA_PTR; 79 80 /* add board specific code here */ 81 int board_init(void) 82 { 83 int id_pfr1, ret; 84 85 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 86 87 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 88 debug("id_pfr1: 0x%08x\n", id_pfr1); 89 /* Generic Timer Extension available? */ 90 if ((id_pfr1 >> 16) & 0xf) { 91 debug("Setting CNTFRQ\n"); 92 /* CNTFRQ == 24 MHz */ 93 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); 94 } 95 96 ret = axp_gpio_init(); 97 if (ret) 98 return ret; 99 100 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 101 return soft_i2c_board_init(); 102 } 103 104 int dram_init(void) 105 { 106 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 107 108 return 0; 109 } 110 111 #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) 112 static void nand_pinmux_setup(void) 113 { 114 unsigned int pin; 115 116 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) 117 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 118 119 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I 120 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) 121 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 122 #endif 123 /* sun4i / sun7i do have a PC23, but it is not used for nand, 124 * only sun7i has a PC24 */ 125 #ifdef CONFIG_MACH_SUN7I 126 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 127 #endif 128 } 129 130 static void nand_clock_setup(void) 131 { 132 struct sunxi_ccm_reg *const ccm = 133 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 134 135 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 136 #ifdef CONFIG_MACH_SUN9I 137 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); 138 #else 139 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); 140 #endif 141 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 142 } 143 144 void board_nand_init(void) 145 { 146 nand_pinmux_setup(); 147 nand_clock_setup(); 148 } 149 #endif 150 151 #ifdef CONFIG_GENERIC_MMC 152 static void mmc_pinmux_setup(int sdc) 153 { 154 unsigned int pin; 155 __maybe_unused int pins; 156 157 switch (sdc) { 158 case 0: 159 /* SDC0: PF0-PF5 */ 160 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 161 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 162 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 163 sunxi_gpio_set_drv(pin, 2); 164 } 165 break; 166 167 case 1: 168 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 169 170 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 171 if (pins == SUNXI_GPIO_H) { 172 /* SDC1: PH22-PH-27 */ 173 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 174 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 175 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 176 sunxi_gpio_set_drv(pin, 2); 177 } 178 } else { 179 /* SDC1: PG0-PG5 */ 180 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 181 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 182 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 183 sunxi_gpio_set_drv(pin, 2); 184 } 185 } 186 #elif defined(CONFIG_MACH_SUN5I) 187 /* SDC1: PG3-PG8 */ 188 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 189 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 190 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 191 sunxi_gpio_set_drv(pin, 2); 192 } 193 #elif defined(CONFIG_MACH_SUN6I) 194 /* SDC1: PG0-PG5 */ 195 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 196 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 197 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 198 sunxi_gpio_set_drv(pin, 2); 199 } 200 #elif defined(CONFIG_MACH_SUN8I) 201 if (pins == SUNXI_GPIO_D) { 202 /* SDC1: PD2-PD7 */ 203 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 204 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 205 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 206 sunxi_gpio_set_drv(pin, 2); 207 } 208 } else { 209 /* SDC1: PG0-PG5 */ 210 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 211 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 212 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 213 sunxi_gpio_set_drv(pin, 2); 214 } 215 } 216 #endif 217 break; 218 219 case 2: 220 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 221 222 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 223 /* SDC2: PC6-PC11 */ 224 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 225 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 226 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 227 sunxi_gpio_set_drv(pin, 2); 228 } 229 #elif defined(CONFIG_MACH_SUN5I) 230 if (pins == SUNXI_GPIO_E) { 231 /* SDC2: PE4-PE9 */ 232 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 233 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 234 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 235 sunxi_gpio_set_drv(pin, 2); 236 } 237 } else { 238 /* SDC2: PC6-PC15 */ 239 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 240 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 241 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 242 sunxi_gpio_set_drv(pin, 2); 243 } 244 } 245 #elif defined(CONFIG_MACH_SUN6I) 246 if (pins == SUNXI_GPIO_A) { 247 /* SDC2: PA9-PA14 */ 248 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 249 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 250 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 251 sunxi_gpio_set_drv(pin, 2); 252 } 253 } else { 254 /* SDC2: PC6-PC15, PC24 */ 255 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 256 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 257 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 258 sunxi_gpio_set_drv(pin, 2); 259 } 260 261 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 262 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 263 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 264 } 265 #elif defined(CONFIG_MACH_SUN8I) 266 /* SDC2: PC5-PC6, PC8-PC16 */ 267 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 268 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 269 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 270 sunxi_gpio_set_drv(pin, 2); 271 } 272 273 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 274 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 275 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 276 sunxi_gpio_set_drv(pin, 2); 277 } 278 #endif 279 break; 280 281 case 3: 282 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 283 284 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 285 /* SDC3: PI4-PI9 */ 286 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 287 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 288 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 289 sunxi_gpio_set_drv(pin, 2); 290 } 291 #elif defined(CONFIG_MACH_SUN6I) 292 if (pins == SUNXI_GPIO_A) { 293 /* SDC3: PA9-PA14 */ 294 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 295 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 296 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 297 sunxi_gpio_set_drv(pin, 2); 298 } 299 } else { 300 /* SDC3: PC6-PC15, PC24 */ 301 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 302 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 303 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 304 sunxi_gpio_set_drv(pin, 2); 305 } 306 307 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 308 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 309 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 310 } 311 #endif 312 break; 313 314 default: 315 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 316 break; 317 } 318 } 319 320 int board_mmc_init(bd_t *bis) 321 { 322 __maybe_unused struct mmc *mmc0, *mmc1; 323 __maybe_unused char buf[512]; 324 325 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 326 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 327 if (!mmc0) 328 return -1; 329 330 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 331 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 332 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 333 if (!mmc1) 334 return -1; 335 #endif 336 337 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 338 /* 339 * On systems with an emmc (mmc2), figure out if we are booting from 340 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. 341 * are searched there first. Note we only do this for u-boot proper, 342 * not for the SPL, see spl_boot_device(). 343 */ 344 if (!sunxi_mmc_has_egon_boot_signature(mmc0) && 345 sunxi_mmc_has_egon_boot_signature(mmc1)) { 346 /* Booting from emmc / mmc2, swap */ 347 mmc0->block_dev.dev = 1; 348 mmc1->block_dev.dev = 0; 349 } 350 #endif 351 352 return 0; 353 } 354 #endif 355 356 void i2c_init_board(void) 357 { 358 #ifdef CONFIG_I2C0_ENABLE 359 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) 360 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 361 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 362 clock_twi_onoff(0, 1); 363 #elif defined(CONFIG_MACH_SUN6I) 364 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 365 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 366 clock_twi_onoff(0, 1); 367 #elif defined(CONFIG_MACH_SUN8I) 368 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 369 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 370 clock_twi_onoff(0, 1); 371 #endif 372 #endif 373 374 #ifdef CONFIG_I2C1_ENABLE 375 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 376 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 377 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 378 clock_twi_onoff(1, 1); 379 #elif defined(CONFIG_MACH_SUN5I) 380 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 381 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 382 clock_twi_onoff(1, 1); 383 #elif defined(CONFIG_MACH_SUN6I) 384 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 385 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 386 clock_twi_onoff(1, 1); 387 #elif defined(CONFIG_MACH_SUN8I) 388 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 389 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 390 clock_twi_onoff(1, 1); 391 #endif 392 #endif 393 394 #ifdef CONFIG_I2C2_ENABLE 395 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 396 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 397 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 398 clock_twi_onoff(2, 1); 399 #elif defined(CONFIG_MACH_SUN5I) 400 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 401 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 402 clock_twi_onoff(2, 1); 403 #elif defined(CONFIG_MACH_SUN6I) 404 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 405 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 406 clock_twi_onoff(2, 1); 407 #elif defined(CONFIG_MACH_SUN8I) 408 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 409 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 410 clock_twi_onoff(2, 1); 411 #endif 412 #endif 413 414 #ifdef CONFIG_I2C3_ENABLE 415 #if defined(CONFIG_MACH_SUN6I) 416 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 417 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 418 clock_twi_onoff(3, 1); 419 #elif defined(CONFIG_MACH_SUN7I) 420 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 421 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 422 clock_twi_onoff(3, 1); 423 #endif 424 #endif 425 426 #ifdef CONFIG_I2C4_ENABLE 427 #if defined(CONFIG_MACH_SUN7I) 428 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 429 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 430 clock_twi_onoff(4, 1); 431 #endif 432 #endif 433 } 434 435 #ifdef CONFIG_SPL_BUILD 436 void sunxi_board_init(void) 437 { 438 int power_failed = 0; 439 unsigned long ramsize; 440 441 #ifdef CONFIG_AXP152_POWER 442 power_failed = axp152_init(); 443 power_failed |= axp152_set_dcdc2(1400); 444 power_failed |= axp152_set_dcdc3(1500); 445 power_failed |= axp152_set_dcdc4(1250); 446 power_failed |= axp152_set_ldo2(3000); 447 #endif 448 #ifdef CONFIG_AXP209_POWER 449 power_failed |= axp209_init(); 450 power_failed |= axp209_set_dcdc2(1400); 451 power_failed |= axp209_set_dcdc3(1250); 452 power_failed |= axp209_set_ldo2(3000); 453 power_failed |= axp209_set_ldo3(2800); 454 power_failed |= axp209_set_ldo4(2800); 455 #endif 456 #ifdef CONFIG_AXP221_POWER 457 power_failed = axp221_init(); 458 power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT); 459 power_failed |= axp221_set_dcdc2(CONFIG_AXP221_DCDC2_VOLT); 460 power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */ 461 #ifdef CONFIG_MACH_SUN6I 462 power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */ 463 #else 464 power_failed |= axp221_set_dcdc4(0); /* A23:unused */ 465 #endif 466 power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */ 467 power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); 468 power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); 469 power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); 470 power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); 471 power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); 472 power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT); 473 #endif 474 475 printf("DRAM:"); 476 ramsize = sunxi_dram_init(); 477 printf(" %lu MiB\n", ramsize >> 20); 478 if (!ramsize) 479 hang(); 480 481 /* 482 * Only clock up the CPU to full speed if we are reasonably 483 * assured it's being powered with suitable core voltage 484 */ 485 if (!power_failed) 486 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 487 else 488 printf("Failed to set core voltage! Can't set CPU frequency\n"); 489 } 490 #endif 491 492 #ifdef CONFIG_USB_GADGET 493 int g_dnl_board_usb_cable_connected(void) 494 { 495 return sunxi_usb_phy_vbus_detect(0); 496 } 497 #endif 498 499 #ifdef CONFIG_SERIAL_TAG 500 void get_board_serial(struct tag_serialnr *serialnr) 501 { 502 char *serial_string; 503 unsigned long long serial; 504 505 serial_string = getenv("serial#"); 506 507 if (serial_string) { 508 serial = simple_strtoull(serial_string, NULL, 16); 509 510 serialnr->high = (unsigned int) (serial >> 32); 511 serialnr->low = (unsigned int) (serial & 0xffffffff); 512 } else { 513 serialnr->high = 0; 514 serialnr->low = 0; 515 } 516 } 517 #endif 518 519 #ifdef CONFIG_MISC_INIT_R 520 int misc_init_r(void) 521 { 522 char serial_string[17] = { 0 }; 523 unsigned int sid[4]; 524 uint8_t mac_addr[6]; 525 int ret; 526 527 ret = sunxi_get_sid(sid); 528 if (ret == 0 && sid[0] != 0 && sid[3] != 0) { 529 if (!getenv("ethaddr")) { 530 /* Non OUI / registered MAC address */ 531 mac_addr[0] = 0x02; 532 mac_addr[1] = (sid[0] >> 0) & 0xff; 533 mac_addr[2] = (sid[3] >> 24) & 0xff; 534 mac_addr[3] = (sid[3] >> 16) & 0xff; 535 mac_addr[4] = (sid[3] >> 8) & 0xff; 536 mac_addr[5] = (sid[3] >> 0) & 0xff; 537 538 eth_setenv_enetaddr("ethaddr", mac_addr); 539 } 540 541 if (!getenv("serial#")) { 542 snprintf(serial_string, sizeof(serial_string), 543 "%08x%08x", sid[0], sid[3]); 544 545 setenv("serial#", serial_string); 546 } 547 } 548 549 #ifndef CONFIG_MACH_SUN9I 550 ret = sunxi_usb_phy_probe(); 551 if (ret) 552 return ret; 553 #endif 554 sunxi_musb_board_init(); 555 556 return 0; 557 } 558 #endif 559 560 #ifdef CONFIG_OF_BOARD_SETUP 561 int ft_board_setup(void *blob, bd_t *bd) 562 { 563 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 564 return sunxi_simplefb_setup(blob); 565 #endif 566 } 567 #endif /* CONFIG_OF_BOARD_SETUP */ 568