1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #include <axp_pmic.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/display.h> 20 #include <asm/arch/dram.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mmc.h> 23 #include <asm/arch/usb_phy.h> 24 #ifndef CONFIG_ARM64 25 #include <asm/armv7.h> 26 #endif 27 #include <asm/gpio.h> 28 #include <asm/io.h> 29 #include <nand.h> 30 #include <net.h> 31 #include <sy8106a.h> 32 33 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 34 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 35 int soft_i2c_gpio_sda; 36 int soft_i2c_gpio_scl; 37 38 static int soft_i2c_board_init(void) 39 { 40 int ret; 41 42 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 43 if (soft_i2c_gpio_sda < 0) { 44 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 45 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 46 return soft_i2c_gpio_sda; 47 } 48 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 49 if (ret) { 50 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 51 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 52 return ret; 53 } 54 55 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 56 if (soft_i2c_gpio_scl < 0) { 57 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 58 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 59 return soft_i2c_gpio_scl; 60 } 61 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 62 if (ret) { 63 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 64 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 65 return ret; 66 } 67 68 return 0; 69 } 70 #else 71 static int soft_i2c_board_init(void) { return 0; } 72 #endif 73 74 DECLARE_GLOBAL_DATA_PTR; 75 76 /* add board specific code here */ 77 int board_init(void) 78 { 79 __maybe_unused int id_pfr1, ret; 80 81 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 82 83 #ifndef CONFIG_ARM64 84 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 85 debug("id_pfr1: 0x%08x\n", id_pfr1); 86 /* Generic Timer Extension available? */ 87 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { 88 uint32_t freq; 89 90 debug("Setting CNTFRQ\n"); 91 92 /* 93 * CNTFRQ is a secure register, so we will crash if we try to 94 * write this from the non-secure world (read is OK, though). 95 * In case some bootcode has already set the correct value, 96 * we avoid the risk of writing to it. 97 */ 98 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); 99 if (freq != CONFIG_TIMER_CLK_FREQ) { 100 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", 101 freq, CONFIG_TIMER_CLK_FREQ); 102 #ifdef CONFIG_NON_SECURE 103 printf("arch timer frequency is wrong, but cannot adjust it\n"); 104 #else 105 asm volatile("mcr p15, 0, %0, c14, c0, 0" 106 : : "r"(CONFIG_TIMER_CLK_FREQ)); 107 #endif 108 } 109 } 110 #endif /* !CONFIG_ARM64 */ 111 112 ret = axp_gpio_init(); 113 if (ret) 114 return ret; 115 116 #ifdef CONFIG_SATAPWR 117 gpio_request(CONFIG_SATAPWR, "satapwr"); 118 gpio_direction_output(CONFIG_SATAPWR, 1); 119 #endif 120 #ifdef CONFIG_MACPWR 121 gpio_request(CONFIG_MACPWR, "macpwr"); 122 gpio_direction_output(CONFIG_MACPWR, 1); 123 #endif 124 125 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 126 return soft_i2c_board_init(); 127 } 128 129 int dram_init(void) 130 { 131 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 132 133 return 0; 134 } 135 136 #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) 137 static void nand_pinmux_setup(void) 138 { 139 unsigned int pin; 140 141 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) 142 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 143 144 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I 145 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) 146 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 147 #endif 148 /* sun4i / sun7i do have a PC23, but it is not used for nand, 149 * only sun7i has a PC24 */ 150 #ifdef CONFIG_MACH_SUN7I 151 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 152 #endif 153 } 154 155 static void nand_clock_setup(void) 156 { 157 struct sunxi_ccm_reg *const ccm = 158 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 159 160 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 161 #ifdef CONFIG_MACH_SUN9I 162 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); 163 #else 164 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); 165 #endif 166 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 167 } 168 169 void board_nand_init(void) 170 { 171 nand_pinmux_setup(); 172 nand_clock_setup(); 173 } 174 #endif 175 176 #ifdef CONFIG_GENERIC_MMC 177 static void mmc_pinmux_setup(int sdc) 178 { 179 unsigned int pin; 180 __maybe_unused int pins; 181 182 switch (sdc) { 183 case 0: 184 /* SDC0: PF0-PF5 */ 185 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 186 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 187 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 188 sunxi_gpio_set_drv(pin, 2); 189 } 190 break; 191 192 case 1: 193 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 194 195 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 196 if (pins == SUNXI_GPIO_H) { 197 /* SDC1: PH22-PH-27 */ 198 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 199 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 200 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 201 sunxi_gpio_set_drv(pin, 2); 202 } 203 } else { 204 /* SDC1: PG0-PG5 */ 205 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 206 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 207 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 208 sunxi_gpio_set_drv(pin, 2); 209 } 210 } 211 #elif defined(CONFIG_MACH_SUN5I) 212 /* SDC1: PG3-PG8 */ 213 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 214 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 215 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 216 sunxi_gpio_set_drv(pin, 2); 217 } 218 #elif defined(CONFIG_MACH_SUN6I) 219 /* SDC1: PG0-PG5 */ 220 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 221 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 222 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 223 sunxi_gpio_set_drv(pin, 2); 224 } 225 #elif defined(CONFIG_MACH_SUN8I) 226 if (pins == SUNXI_GPIO_D) { 227 /* SDC1: PD2-PD7 */ 228 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 229 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 230 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 231 sunxi_gpio_set_drv(pin, 2); 232 } 233 } else { 234 /* SDC1: PG0-PG5 */ 235 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 236 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 237 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 238 sunxi_gpio_set_drv(pin, 2); 239 } 240 } 241 #endif 242 break; 243 244 case 2: 245 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 246 247 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 248 /* SDC2: PC6-PC11 */ 249 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 250 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 251 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 252 sunxi_gpio_set_drv(pin, 2); 253 } 254 #elif defined(CONFIG_MACH_SUN5I) 255 if (pins == SUNXI_GPIO_E) { 256 /* SDC2: PE4-PE9 */ 257 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 258 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 259 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 260 sunxi_gpio_set_drv(pin, 2); 261 } 262 } else { 263 /* SDC2: PC6-PC15 */ 264 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 265 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 266 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 267 sunxi_gpio_set_drv(pin, 2); 268 } 269 } 270 #elif defined(CONFIG_MACH_SUN6I) 271 if (pins == SUNXI_GPIO_A) { 272 /* SDC2: PA9-PA14 */ 273 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 274 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 275 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 276 sunxi_gpio_set_drv(pin, 2); 277 } 278 } else { 279 /* SDC2: PC6-PC15, PC24 */ 280 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 281 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 282 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 283 sunxi_gpio_set_drv(pin, 2); 284 } 285 286 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 287 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 288 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 289 } 290 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) 291 /* SDC2: PC5-PC6, PC8-PC16 */ 292 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 293 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 294 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 295 sunxi_gpio_set_drv(pin, 2); 296 } 297 298 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 299 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 300 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 301 sunxi_gpio_set_drv(pin, 2); 302 } 303 #endif 304 break; 305 306 case 3: 307 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 308 309 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 310 /* SDC3: PI4-PI9 */ 311 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 312 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 313 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 314 sunxi_gpio_set_drv(pin, 2); 315 } 316 #elif defined(CONFIG_MACH_SUN6I) 317 if (pins == SUNXI_GPIO_A) { 318 /* SDC3: PA9-PA14 */ 319 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 320 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 321 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 322 sunxi_gpio_set_drv(pin, 2); 323 } 324 } else { 325 /* SDC3: PC6-PC15, PC24 */ 326 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 327 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 328 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 329 sunxi_gpio_set_drv(pin, 2); 330 } 331 332 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 333 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 334 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 335 } 336 #endif 337 break; 338 339 default: 340 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 341 break; 342 } 343 } 344 345 int board_mmc_init(bd_t *bis) 346 { 347 __maybe_unused struct mmc *mmc0, *mmc1; 348 __maybe_unused char buf[512]; 349 350 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 351 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 352 if (!mmc0) 353 return -1; 354 355 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 356 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 357 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 358 if (!mmc1) 359 return -1; 360 #endif 361 362 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 363 /* 364 * On systems with an emmc (mmc2), figure out if we are booting from 365 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. 366 * are searched there first. Note we only do this for u-boot proper, 367 * not for the SPL, see spl_boot_device(). 368 */ 369 if (!sunxi_mmc_has_egon_boot_signature(mmc0) && 370 sunxi_mmc_has_egon_boot_signature(mmc1)) { 371 /* Booting from emmc / mmc2, swap */ 372 mmc0->block_dev.devnum = 1; 373 mmc1->block_dev.devnum = 0; 374 } 375 #endif 376 377 return 0; 378 } 379 #endif 380 381 void i2c_init_board(void) 382 { 383 #ifdef CONFIG_I2C0_ENABLE 384 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) 385 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 386 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 387 clock_twi_onoff(0, 1); 388 #elif defined(CONFIG_MACH_SUN6I) 389 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 390 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 391 clock_twi_onoff(0, 1); 392 #elif defined(CONFIG_MACH_SUN8I) 393 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 394 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 395 clock_twi_onoff(0, 1); 396 #endif 397 #endif 398 399 #ifdef CONFIG_I2C1_ENABLE 400 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 401 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 402 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 403 clock_twi_onoff(1, 1); 404 #elif defined(CONFIG_MACH_SUN5I) 405 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 406 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 407 clock_twi_onoff(1, 1); 408 #elif defined(CONFIG_MACH_SUN6I) 409 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 410 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 411 clock_twi_onoff(1, 1); 412 #elif defined(CONFIG_MACH_SUN8I) 413 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 414 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 415 clock_twi_onoff(1, 1); 416 #endif 417 #endif 418 419 #ifdef CONFIG_I2C2_ENABLE 420 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 421 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 422 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 423 clock_twi_onoff(2, 1); 424 #elif defined(CONFIG_MACH_SUN5I) 425 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 426 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 427 clock_twi_onoff(2, 1); 428 #elif defined(CONFIG_MACH_SUN6I) 429 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 430 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 431 clock_twi_onoff(2, 1); 432 #elif defined(CONFIG_MACH_SUN8I) 433 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 434 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 435 clock_twi_onoff(2, 1); 436 #endif 437 #endif 438 439 #ifdef CONFIG_I2C3_ENABLE 440 #if defined(CONFIG_MACH_SUN6I) 441 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 442 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 443 clock_twi_onoff(3, 1); 444 #elif defined(CONFIG_MACH_SUN7I) 445 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 446 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 447 clock_twi_onoff(3, 1); 448 #endif 449 #endif 450 451 #ifdef CONFIG_I2C4_ENABLE 452 #if defined(CONFIG_MACH_SUN7I) 453 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 454 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 455 clock_twi_onoff(4, 1); 456 #endif 457 #endif 458 459 #ifdef CONFIG_R_I2C_ENABLE 460 clock_twi_onoff(5, 1); 461 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); 462 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); 463 #endif 464 } 465 466 #ifdef CONFIG_SPL_BUILD 467 void sunxi_board_init(void) 468 { 469 int power_failed = 0; 470 unsigned long ramsize; 471 472 #ifdef CONFIG_SY8106A_POWER 473 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); 474 #endif 475 476 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 477 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 478 defined CONFIG_AXP818_POWER 479 power_failed = axp_init(); 480 481 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 482 defined CONFIG_AXP818_POWER 483 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); 484 #endif 485 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); 486 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); 487 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) 488 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); 489 #endif 490 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 491 defined CONFIG_AXP818_POWER 492 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); 493 #endif 494 495 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 496 defined CONFIG_AXP818_POWER 497 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); 498 #endif 499 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); 500 #if !defined(CONFIG_AXP152_POWER) 501 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); 502 #endif 503 #ifdef CONFIG_AXP209_POWER 504 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); 505 #endif 506 507 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ 508 defined(CONFIG_AXP818_POWER) 509 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); 510 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); 511 #if !defined CONFIG_AXP809_POWER 512 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); 513 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); 514 #endif 515 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); 516 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); 517 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); 518 #endif 519 520 #ifdef CONFIG_AXP818_POWER 521 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); 522 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); 523 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); 524 #endif 525 526 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 527 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); 528 #endif 529 #endif 530 printf("DRAM:"); 531 ramsize = sunxi_dram_init(); 532 printf(" %lu MiB\n", ramsize >> 20); 533 if (!ramsize) 534 hang(); 535 536 /* 537 * Only clock up the CPU to full speed if we are reasonably 538 * assured it's being powered with suitable core voltage 539 */ 540 if (!power_failed) 541 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 542 else 543 printf("Failed to set core voltage! Can't set CPU frequency\n"); 544 } 545 #endif 546 547 #ifdef CONFIG_USB_GADGET 548 int g_dnl_board_usb_cable_connected(void) 549 { 550 return sunxi_usb_phy_vbus_detect(0); 551 } 552 #endif 553 554 #ifdef CONFIG_SERIAL_TAG 555 void get_board_serial(struct tag_serialnr *serialnr) 556 { 557 char *serial_string; 558 unsigned long long serial; 559 560 serial_string = getenv("serial#"); 561 562 if (serial_string) { 563 serial = simple_strtoull(serial_string, NULL, 16); 564 565 serialnr->high = (unsigned int) (serial >> 32); 566 serialnr->low = (unsigned int) (serial & 0xffffffff); 567 } else { 568 serialnr->high = 0; 569 serialnr->low = 0; 570 } 571 } 572 #endif 573 574 #if !defined(CONFIG_SPL_BUILD) 575 #include <asm/arch/spl.h> 576 577 /* 578 * Check the SPL header for the "sunxi" variant. If found: parse values 579 * that might have been passed by the loader ("fel" utility), and update 580 * the environment accordingly. 581 */ 582 static void parse_spl_header(const uint32_t spl_addr) 583 { 584 struct boot_file_head *spl = (void *)(ulong)spl_addr; 585 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) { 586 uint8_t spl_header_version = spl->spl_signature[3]; 587 if (spl_header_version == SPL_HEADER_VERSION) { 588 if (spl->fel_script_address) 589 setenv_hex("fel_scriptaddr", 590 spl->fel_script_address); 591 return; 592 } 593 printf("sunxi SPL version mismatch: expected %u, got %u\n", 594 SPL_HEADER_VERSION, spl_header_version); 595 } 596 } 597 #endif 598 599 #ifdef CONFIG_MISC_INIT_R 600 int misc_init_r(void) 601 { 602 char serial_string[17] = { 0 }; 603 unsigned int sid[4]; 604 uint8_t mac_addr[6]; 605 int ret; 606 607 #if !defined(CONFIG_SPL_BUILD) 608 setenv("fel_booted", NULL); 609 setenv("fel_scriptaddr", NULL); 610 /* determine if we are running in FEL mode */ 611 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ 612 setenv("fel_booted", "1"); 613 parse_spl_header(SPL_ADDR); 614 } 615 #endif 616 617 ret = sunxi_get_sid(sid); 618 if (ret == 0 && sid[0] != 0 && sid[3] != 0) { 619 if (!getenv("ethaddr")) { 620 /* Non OUI / registered MAC address */ 621 mac_addr[0] = 0x02; 622 mac_addr[1] = (sid[0] >> 0) & 0xff; 623 mac_addr[2] = (sid[3] >> 24) & 0xff; 624 mac_addr[3] = (sid[3] >> 16) & 0xff; 625 mac_addr[4] = (sid[3] >> 8) & 0xff; 626 mac_addr[5] = (sid[3] >> 0) & 0xff; 627 628 eth_setenv_enetaddr("ethaddr", mac_addr); 629 } 630 631 if (!getenv("serial#")) { 632 snprintf(serial_string, sizeof(serial_string), 633 "%08x%08x", sid[0], sid[3]); 634 635 setenv("serial#", serial_string); 636 } 637 } 638 639 #ifndef CONFIG_MACH_SUN9I 640 ret = sunxi_usb_phy_probe(); 641 if (ret) 642 return ret; 643 #endif 644 sunxi_musb_board_init(); 645 646 return 0; 647 } 648 #endif 649 650 int ft_board_setup(void *blob, bd_t *bd) 651 { 652 int __maybe_unused r; 653 654 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 655 r = sunxi_simplefb_setup(blob); 656 if (r) 657 return r; 658 #endif 659 return 0; 660 } 661