1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #include <axp_pmic.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/display.h> 20 #include <asm/arch/dram.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mmc.h> 23 #include <asm/arch/spl.h> 24 #include <asm/arch/usb_phy.h> 25 #ifndef CONFIG_ARM64 26 #include <asm/armv7.h> 27 #endif 28 #include <asm/gpio.h> 29 #include <asm/io.h> 30 #include <crc.h> 31 #include <environment.h> 32 #include <libfdt.h> 33 #include <nand.h> 34 #include <net.h> 35 #include <sy8106a.h> 36 37 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 38 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 39 int soft_i2c_gpio_sda; 40 int soft_i2c_gpio_scl; 41 42 static int soft_i2c_board_init(void) 43 { 44 int ret; 45 46 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 47 if (soft_i2c_gpio_sda < 0) { 48 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 49 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 50 return soft_i2c_gpio_sda; 51 } 52 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 53 if (ret) { 54 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 55 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 56 return ret; 57 } 58 59 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 60 if (soft_i2c_gpio_scl < 0) { 61 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 62 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 63 return soft_i2c_gpio_scl; 64 } 65 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 66 if (ret) { 67 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 68 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 69 return ret; 70 } 71 72 return 0; 73 } 74 #else 75 static int soft_i2c_board_init(void) { return 0; } 76 #endif 77 78 DECLARE_GLOBAL_DATA_PTR; 79 80 /* add board specific code here */ 81 int board_init(void) 82 { 83 __maybe_unused int id_pfr1, ret; 84 85 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 86 87 #ifndef CONFIG_ARM64 88 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 89 debug("id_pfr1: 0x%08x\n", id_pfr1); 90 /* Generic Timer Extension available? */ 91 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { 92 uint32_t freq; 93 94 debug("Setting CNTFRQ\n"); 95 96 /* 97 * CNTFRQ is a secure register, so we will crash if we try to 98 * write this from the non-secure world (read is OK, though). 99 * In case some bootcode has already set the correct value, 100 * we avoid the risk of writing to it. 101 */ 102 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); 103 if (freq != CONFIG_TIMER_CLK_FREQ) { 104 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", 105 freq, CONFIG_TIMER_CLK_FREQ); 106 #ifdef CONFIG_NON_SECURE 107 printf("arch timer frequency is wrong, but cannot adjust it\n"); 108 #else 109 asm volatile("mcr p15, 0, %0, c14, c0, 0" 110 : : "r"(CONFIG_TIMER_CLK_FREQ)); 111 #endif 112 } 113 } 114 #endif /* !CONFIG_ARM64 */ 115 116 ret = axp_gpio_init(); 117 if (ret) 118 return ret; 119 120 #ifdef CONFIG_SATAPWR 121 gpio_request(CONFIG_SATAPWR, "satapwr"); 122 gpio_direction_output(CONFIG_SATAPWR, 1); 123 #endif 124 #ifdef CONFIG_MACPWR 125 gpio_request(CONFIG_MACPWR, "macpwr"); 126 gpio_direction_output(CONFIG_MACPWR, 1); 127 #endif 128 129 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 130 return soft_i2c_board_init(); 131 } 132 133 int dram_init(void) 134 { 135 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 136 137 return 0; 138 } 139 140 #if defined(CONFIG_NAND_SUNXI) 141 static void nand_pinmux_setup(void) 142 { 143 unsigned int pin; 144 145 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) 146 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 147 148 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I 149 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) 150 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 151 #endif 152 /* sun4i / sun7i do have a PC23, but it is not used for nand, 153 * only sun7i has a PC24 */ 154 #ifdef CONFIG_MACH_SUN7I 155 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 156 #endif 157 } 158 159 static void nand_clock_setup(void) 160 { 161 struct sunxi_ccm_reg *const ccm = 162 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 163 164 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 165 #ifdef CONFIG_MACH_SUN9I 166 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); 167 #else 168 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); 169 #endif 170 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 171 } 172 173 void board_nand_init(void) 174 { 175 nand_pinmux_setup(); 176 nand_clock_setup(); 177 #ifndef CONFIG_SPL_BUILD 178 sunxi_nand_init(); 179 #endif 180 } 181 #endif 182 183 #ifdef CONFIG_GENERIC_MMC 184 static void mmc_pinmux_setup(int sdc) 185 { 186 unsigned int pin; 187 __maybe_unused int pins; 188 189 switch (sdc) { 190 case 0: 191 /* SDC0: PF0-PF5 */ 192 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 193 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 194 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 195 sunxi_gpio_set_drv(pin, 2); 196 } 197 break; 198 199 case 1: 200 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 201 202 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 203 if (pins == SUNXI_GPIO_H) { 204 /* SDC1: PH22-PH-27 */ 205 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 206 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 207 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 208 sunxi_gpio_set_drv(pin, 2); 209 } 210 } else { 211 /* SDC1: PG0-PG5 */ 212 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 213 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 214 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 215 sunxi_gpio_set_drv(pin, 2); 216 } 217 } 218 #elif defined(CONFIG_MACH_SUN5I) 219 /* SDC1: PG3-PG8 */ 220 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 221 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 222 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 223 sunxi_gpio_set_drv(pin, 2); 224 } 225 #elif defined(CONFIG_MACH_SUN6I) 226 /* SDC1: PG0-PG5 */ 227 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 228 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 229 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 230 sunxi_gpio_set_drv(pin, 2); 231 } 232 #elif defined(CONFIG_MACH_SUN8I) 233 if (pins == SUNXI_GPIO_D) { 234 /* SDC1: PD2-PD7 */ 235 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 236 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 237 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 238 sunxi_gpio_set_drv(pin, 2); 239 } 240 } else { 241 /* SDC1: PG0-PG5 */ 242 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 243 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 244 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 245 sunxi_gpio_set_drv(pin, 2); 246 } 247 } 248 #endif 249 break; 250 251 case 2: 252 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 253 254 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 255 /* SDC2: PC6-PC11 */ 256 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 257 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 258 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 259 sunxi_gpio_set_drv(pin, 2); 260 } 261 #elif defined(CONFIG_MACH_SUN5I) 262 if (pins == SUNXI_GPIO_E) { 263 /* SDC2: PE4-PE9 */ 264 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 265 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 266 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 267 sunxi_gpio_set_drv(pin, 2); 268 } 269 } else { 270 /* SDC2: PC6-PC15 */ 271 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 272 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 273 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 274 sunxi_gpio_set_drv(pin, 2); 275 } 276 } 277 #elif defined(CONFIG_MACH_SUN6I) 278 if (pins == SUNXI_GPIO_A) { 279 /* SDC2: PA9-PA14 */ 280 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 281 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 282 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 283 sunxi_gpio_set_drv(pin, 2); 284 } 285 } else { 286 /* SDC2: PC6-PC15, PC24 */ 287 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 288 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 289 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 290 sunxi_gpio_set_drv(pin, 2); 291 } 292 293 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 294 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 295 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 296 } 297 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) 298 /* SDC2: PC5-PC6, PC8-PC16 */ 299 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 300 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 301 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 302 sunxi_gpio_set_drv(pin, 2); 303 } 304 305 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 306 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 307 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 308 sunxi_gpio_set_drv(pin, 2); 309 } 310 #endif 311 break; 312 313 case 3: 314 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 315 316 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 317 /* SDC3: PI4-PI9 */ 318 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 319 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 320 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 321 sunxi_gpio_set_drv(pin, 2); 322 } 323 #elif defined(CONFIG_MACH_SUN6I) 324 if (pins == SUNXI_GPIO_A) { 325 /* SDC3: PA9-PA14 */ 326 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 327 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 328 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 329 sunxi_gpio_set_drv(pin, 2); 330 } 331 } else { 332 /* SDC3: PC6-PC15, PC24 */ 333 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 334 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 335 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 336 sunxi_gpio_set_drv(pin, 2); 337 } 338 339 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 340 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 341 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 342 } 343 #endif 344 break; 345 346 default: 347 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 348 break; 349 } 350 } 351 352 int board_mmc_init(bd_t *bis) 353 { 354 __maybe_unused struct mmc *mmc0, *mmc1; 355 __maybe_unused char buf[512]; 356 357 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 358 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 359 if (!mmc0) 360 return -1; 361 362 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 363 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 364 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 365 if (!mmc1) 366 return -1; 367 #endif 368 369 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 370 /* 371 * On systems with an emmc (mmc2), figure out if we are booting from 372 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. 373 * are searched there first. Note we only do this for u-boot proper, 374 * not for the SPL, see spl_boot_device(). 375 */ 376 if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) { 377 /* Booting from emmc / mmc2, swap */ 378 mmc0->block_dev.devnum = 1; 379 mmc1->block_dev.devnum = 0; 380 } 381 #endif 382 383 return 0; 384 } 385 #endif 386 387 void i2c_init_board(void) 388 { 389 #ifdef CONFIG_I2C0_ENABLE 390 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) 391 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 392 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 393 clock_twi_onoff(0, 1); 394 #elif defined(CONFIG_MACH_SUN6I) 395 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 396 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 397 clock_twi_onoff(0, 1); 398 #elif defined(CONFIG_MACH_SUN8I) 399 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 400 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 401 clock_twi_onoff(0, 1); 402 #endif 403 #endif 404 405 #ifdef CONFIG_I2C1_ENABLE 406 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 407 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 408 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 409 clock_twi_onoff(1, 1); 410 #elif defined(CONFIG_MACH_SUN5I) 411 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 412 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 413 clock_twi_onoff(1, 1); 414 #elif defined(CONFIG_MACH_SUN6I) 415 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 416 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 417 clock_twi_onoff(1, 1); 418 #elif defined(CONFIG_MACH_SUN8I) 419 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 420 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 421 clock_twi_onoff(1, 1); 422 #endif 423 #endif 424 425 #ifdef CONFIG_I2C2_ENABLE 426 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 427 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 428 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 429 clock_twi_onoff(2, 1); 430 #elif defined(CONFIG_MACH_SUN5I) 431 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 432 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 433 clock_twi_onoff(2, 1); 434 #elif defined(CONFIG_MACH_SUN6I) 435 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 436 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 437 clock_twi_onoff(2, 1); 438 #elif defined(CONFIG_MACH_SUN8I) 439 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 440 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 441 clock_twi_onoff(2, 1); 442 #endif 443 #endif 444 445 #ifdef CONFIG_I2C3_ENABLE 446 #if defined(CONFIG_MACH_SUN6I) 447 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 448 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 449 clock_twi_onoff(3, 1); 450 #elif defined(CONFIG_MACH_SUN7I) 451 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 452 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 453 clock_twi_onoff(3, 1); 454 #endif 455 #endif 456 457 #ifdef CONFIG_I2C4_ENABLE 458 #if defined(CONFIG_MACH_SUN7I) 459 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 460 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 461 clock_twi_onoff(4, 1); 462 #endif 463 #endif 464 465 #ifdef CONFIG_R_I2C_ENABLE 466 clock_twi_onoff(5, 1); 467 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); 468 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); 469 #endif 470 } 471 472 #ifdef CONFIG_SPL_BUILD 473 void sunxi_board_init(void) 474 { 475 int power_failed = 0; 476 unsigned long ramsize; 477 478 #ifdef CONFIG_SY8106A_POWER 479 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); 480 #endif 481 482 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 483 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 484 defined CONFIG_AXP818_POWER 485 power_failed = axp_init(); 486 487 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 488 defined CONFIG_AXP818_POWER 489 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); 490 #endif 491 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); 492 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); 493 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) 494 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); 495 #endif 496 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 497 defined CONFIG_AXP818_POWER 498 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); 499 #endif 500 501 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 502 defined CONFIG_AXP818_POWER 503 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); 504 #endif 505 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); 506 #if !defined(CONFIG_AXP152_POWER) 507 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); 508 #endif 509 #ifdef CONFIG_AXP209_POWER 510 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); 511 #endif 512 513 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ 514 defined(CONFIG_AXP818_POWER) 515 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); 516 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); 517 #if !defined CONFIG_AXP809_POWER 518 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); 519 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); 520 #endif 521 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); 522 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); 523 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); 524 #endif 525 526 #ifdef CONFIG_AXP818_POWER 527 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); 528 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); 529 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); 530 #endif 531 532 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 533 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); 534 #endif 535 #endif 536 printf("DRAM:"); 537 ramsize = sunxi_dram_init(); 538 printf(" %d MiB\n", (int)(ramsize >> 20)); 539 if (!ramsize) 540 hang(); 541 542 /* 543 * Only clock up the CPU to full speed if we are reasonably 544 * assured it's being powered with suitable core voltage 545 */ 546 if (!power_failed) 547 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 548 else 549 printf("Failed to set core voltage! Can't set CPU frequency\n"); 550 } 551 #endif 552 553 #ifdef CONFIG_USB_GADGET 554 int g_dnl_board_usb_cable_connected(void) 555 { 556 return sunxi_usb_phy_vbus_detect(0); 557 } 558 #endif 559 560 #ifdef CONFIG_SERIAL_TAG 561 void get_board_serial(struct tag_serialnr *serialnr) 562 { 563 char *serial_string; 564 unsigned long long serial; 565 566 serial_string = getenv("serial#"); 567 568 if (serial_string) { 569 serial = simple_strtoull(serial_string, NULL, 16); 570 571 serialnr->high = (unsigned int) (serial >> 32); 572 serialnr->low = (unsigned int) (serial & 0xffffffff); 573 } else { 574 serialnr->high = 0; 575 serialnr->low = 0; 576 } 577 } 578 #endif 579 580 /* 581 * Check the SPL header for the "sunxi" variant. If found: parse values 582 * that might have been passed by the loader ("fel" utility), and update 583 * the environment accordingly. 584 */ 585 static void parse_spl_header(const uint32_t spl_addr) 586 { 587 struct boot_file_head *spl = (void *)(ulong)spl_addr; 588 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0) 589 return; /* signature mismatch, no usable header */ 590 591 uint8_t spl_header_version = spl->spl_signature[3]; 592 if (spl_header_version != SPL_HEADER_VERSION) { 593 printf("sunxi SPL version mismatch: expected %u, got %u\n", 594 SPL_HEADER_VERSION, spl_header_version); 595 return; 596 } 597 if (!spl->fel_script_address) 598 return; 599 600 if (spl->fel_uEnv_length != 0) { 601 /* 602 * data is expected in uEnv.txt compatible format, so "env 603 * import -t" the string(s) at fel_script_address right away. 604 */ 605 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address, 606 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL); 607 return; 608 } 609 /* otherwise assume .scr format (mkimage-type script) */ 610 setenv_hex("fel_scriptaddr", spl->fel_script_address); 611 } 612 613 /* 614 * Note this function gets called multiple times. 615 * It must not make any changes to env variables which already exist. 616 */ 617 static void setup_environment(const void *fdt) 618 { 619 char serial_string[17] = { 0 }; 620 unsigned int sid[4]; 621 uint8_t mac_addr[6]; 622 char ethaddr[16]; 623 int i, ret; 624 625 ret = sunxi_get_sid(sid); 626 if (ret == 0 && sid[0] != 0) { 627 /* 628 * The single words 1 - 3 of the SID have quite a few bits 629 * which are the same on many models, so we take a crc32 630 * of all 3 words, to get a more unique value. 631 * 632 * Note we only do this on newer SoCs as we cannot change 633 * the algorithm on older SoCs since those have been using 634 * fixed mac-addresses based on only using word 3 for a 635 * long time and changing a fixed mac-address with an 636 * u-boot update is not good. 637 */ 638 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ 639 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ 640 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) 641 sid[3] = crc32(0, (unsigned char *)&sid[1], 12); 642 #endif 643 644 /* Ensure the NIC specific bytes of the mac are not all 0 */ 645 if ((sid[3] & 0xffffff) == 0) 646 sid[3] |= 0x800000; 647 648 for (i = 0; i < 4; i++) { 649 sprintf(ethaddr, "ethernet%d", i); 650 if (!fdt_get_alias(fdt, ethaddr)) 651 continue; 652 653 if (i == 0) 654 strcpy(ethaddr, "ethaddr"); 655 else 656 sprintf(ethaddr, "eth%daddr", i); 657 658 if (getenv(ethaddr)) 659 continue; 660 661 /* Non OUI / registered MAC address */ 662 mac_addr[0] = (i << 4) | 0x02; 663 mac_addr[1] = (sid[0] >> 0) & 0xff; 664 mac_addr[2] = (sid[3] >> 24) & 0xff; 665 mac_addr[3] = (sid[3] >> 16) & 0xff; 666 mac_addr[4] = (sid[3] >> 8) & 0xff; 667 mac_addr[5] = (sid[3] >> 0) & 0xff; 668 669 eth_setenv_enetaddr(ethaddr, mac_addr); 670 } 671 672 if (!getenv("serial#")) { 673 snprintf(serial_string, sizeof(serial_string), 674 "%08x%08x", sid[0], sid[3]); 675 676 setenv("serial#", serial_string); 677 } 678 } 679 } 680 681 int misc_init_r(void) 682 { 683 __maybe_unused int ret; 684 685 setenv("fel_booted", NULL); 686 setenv("fel_scriptaddr", NULL); 687 /* determine if we are running in FEL mode */ 688 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ 689 setenv("fel_booted", "1"); 690 parse_spl_header(SPL_ADDR); 691 } 692 693 setup_environment(gd->fdt_blob); 694 695 #ifndef CONFIG_MACH_SUN9I 696 ret = sunxi_usb_phy_probe(); 697 if (ret) 698 return ret; 699 #endif 700 sunxi_musb_board_init(); 701 702 return 0; 703 } 704 705 int ft_board_setup(void *blob, bd_t *bd) 706 { 707 int __maybe_unused r; 708 709 /* 710 * Call setup_environment again in case the boot fdt has 711 * ethernet aliases the u-boot copy does not have. 712 */ 713 setup_environment(blob); 714 715 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 716 r = sunxi_simplefb_setup(blob); 717 if (r) 718 return r; 719 #endif 720 return 0; 721 } 722