1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #ifdef CONFIG_AXP152_POWER 17 #include <axp152.h> 18 #endif 19 #ifdef CONFIG_AXP209_POWER 20 #include <axp209.h> 21 #endif 22 #ifdef CONFIG_AXP221_POWER 23 #include <axp221.h> 24 #endif 25 #include <asm/arch/clock.h> 26 #include <asm/arch/cpu.h> 27 #include <asm/arch/dram.h> 28 #include <asm/arch/gpio.h> 29 #include <asm/arch/mmc.h> 30 #include <asm/io.h> 31 #include <net.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 /* add board specific code here */ 36 int board_init(void) 37 { 38 int id_pfr1; 39 40 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 41 42 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 43 debug("id_pfr1: 0x%08x\n", id_pfr1); 44 /* Generic Timer Extension available? */ 45 if ((id_pfr1 >> 16) & 0xf) { 46 debug("Setting CNTFRQ\n"); 47 /* CNTFRQ == 24 MHz */ 48 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); 49 } 50 51 return 0; 52 } 53 54 int dram_init(void) 55 { 56 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 57 58 return 0; 59 } 60 61 #ifdef CONFIG_GENERIC_MMC 62 static void mmc_pinmux_setup(int sdc) 63 { 64 unsigned int pin; 65 66 switch (sdc) { 67 case 0: 68 /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */ 69 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 70 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0); 71 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 72 sunxi_gpio_set_drv(pin, 2); 73 } 74 break; 75 76 case 1: 77 /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */ 78 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 79 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1); 80 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 81 sunxi_gpio_set_drv(pin, 2); 82 } 83 break; 84 85 case 2: 86 /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */ 87 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 88 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2); 89 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 90 sunxi_gpio_set_drv(pin, 2); 91 } 92 break; 93 94 case 3: 95 /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */ 96 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 97 sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3); 98 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 99 sunxi_gpio_set_drv(pin, 2); 100 } 101 break; 102 103 default: 104 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 105 break; 106 } 107 } 108 109 int board_mmc_init(bd_t *bis) 110 { 111 __maybe_unused struct mmc *mmc0, *mmc1; 112 __maybe_unused char buf[512]; 113 114 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 115 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 116 if (!mmc0) 117 return -1; 118 119 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 120 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 121 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 122 if (!mmc1) 123 return -1; 124 #endif 125 126 #if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 127 /* 128 * Both mmc0 and mmc2 are bootable, figure out where we're booting 129 * from. Try mmc0 first, just like the brom does. 130 */ 131 if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 && 132 mmc0->block_dev.block_read(0, 16, 1, buf) == 1) { 133 buf[12] = 0; 134 if (strcmp(&buf[4], "eGON.BT0") == 0) 135 return 0; 136 } 137 138 /* no bootable card in mmc0, so we must be booting from mmc2, swap */ 139 mmc0->block_dev.dev = 1; 140 mmc1->block_dev.dev = 0; 141 #endif 142 143 return 0; 144 } 145 #endif 146 147 void i2c_init_board(void) 148 { 149 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0); 150 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0); 151 clock_twi_onoff(0, 1); 152 } 153 154 #ifdef CONFIG_SPL_BUILD 155 void sunxi_board_init(void) 156 { 157 int power_failed = 0; 158 unsigned long ramsize; 159 160 #ifdef CONFIG_AXP152_POWER 161 power_failed = axp152_init(); 162 power_failed |= axp152_set_dcdc2(1400); 163 power_failed |= axp152_set_dcdc3(1500); 164 power_failed |= axp152_set_dcdc4(1250); 165 power_failed |= axp152_set_ldo2(3000); 166 #endif 167 #ifdef CONFIG_AXP209_POWER 168 power_failed |= axp209_init(); 169 power_failed |= axp209_set_dcdc2(1400); 170 power_failed |= axp209_set_dcdc3(1250); 171 power_failed |= axp209_set_ldo2(3000); 172 power_failed |= axp209_set_ldo3(2800); 173 power_failed |= axp209_set_ldo4(2800); 174 #endif 175 #ifdef CONFIG_AXP221_POWER 176 power_failed = axp221_init(); 177 power_failed |= axp221_set_dcdc1(3000); 178 power_failed |= axp221_set_dcdc2(1200); 179 power_failed |= axp221_set_dcdc3(1200); 180 power_failed |= axp221_set_dcdc4(1200); 181 power_failed |= axp221_set_dcdc5(1500); 182 #if CONFIG_AXP221_DLDO1_VOLT != -1 183 power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); 184 #endif 185 #if CONFIG_AXP221_DLDO4_VOLT != -1 186 power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); 187 #endif 188 #if CONFIG_AXP221_ALDO1_VOLT != -1 189 power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); 190 #endif 191 #if CONFIG_AXP221_ALDO2_VOLT != -1 192 power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); 193 #endif 194 #if CONFIG_AXP221_ALDO3_VOLT != -1 195 power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); 196 #endif 197 #endif 198 199 printf("DRAM:"); 200 ramsize = sunxi_dram_init(); 201 printf(" %lu MiB\n", ramsize >> 20); 202 if (!ramsize) 203 hang(); 204 205 /* 206 * Only clock up the CPU to full speed if we are reasonably 207 * assured it's being powered with suitable core voltage 208 */ 209 if (!power_failed) 210 clock_set_pll1(CONFIG_CLK_FULL_SPEED); 211 else 212 printf("Failed to set core voltage! Can't set CPU frequency\n"); 213 } 214 #endif 215 216 #ifdef CONFIG_MISC_INIT_R 217 int misc_init_r(void) 218 { 219 if (!getenv("ethaddr")) { 220 uint32_t reg_val = readl(SUNXI_SID_BASE); 221 222 if (reg_val) { 223 uint8_t mac_addr[6]; 224 225 mac_addr[0] = 0x02; /* Non OUI / registered MAC address */ 226 mac_addr[1] = (reg_val >> 0) & 0xff; 227 reg_val = readl(SUNXI_SID_BASE + 0x0c); 228 mac_addr[2] = (reg_val >> 24) & 0xff; 229 mac_addr[3] = (reg_val >> 16) & 0xff; 230 mac_addr[4] = (reg_val >> 8) & 0xff; 231 mac_addr[5] = (reg_val >> 0) & 0xff; 232 233 eth_setenv_enetaddr("ethaddr", mac_addr); 234 } 235 } 236 237 return 0; 238 } 239 #endif 240