1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #ifdef CONFIG_AXP152_POWER 17 #include <axp152.h> 18 #endif 19 #ifdef CONFIG_AXP209_POWER 20 #include <axp209.h> 21 #endif 22 #ifdef CONFIG_AXP221_POWER 23 #include <axp221.h> 24 #endif 25 #ifdef CONFIG_NAND_SUNXI 26 #include <nand.h> 27 #endif 28 #include <asm/arch/clock.h> 29 #include <asm/arch/cpu.h> 30 #include <asm/arch/display.h> 31 #include <asm/arch/dram.h> 32 #include <asm/arch/gpio.h> 33 #include <asm/arch/mmc.h> 34 #include <asm/arch/usb_phy.h> 35 #include <asm/gpio.h> 36 #include <asm/io.h> 37 #include <linux/usb/musb.h> 38 #include <net.h> 39 40 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 41 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 42 int soft_i2c_gpio_sda; 43 int soft_i2c_gpio_scl; 44 45 static int soft_i2c_board_init(void) 46 { 47 int ret; 48 49 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 50 if (soft_i2c_gpio_sda < 0) { 51 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 52 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 53 return soft_i2c_gpio_sda; 54 } 55 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 56 if (ret) { 57 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 58 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 59 return ret; 60 } 61 62 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 63 if (soft_i2c_gpio_scl < 0) { 64 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 65 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 66 return soft_i2c_gpio_scl; 67 } 68 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 69 if (ret) { 70 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 71 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 72 return ret; 73 } 74 75 return 0; 76 } 77 #else 78 static int soft_i2c_board_init(void) { return 0; } 79 #endif 80 81 DECLARE_GLOBAL_DATA_PTR; 82 83 /* add board specific code here */ 84 int board_init(void) 85 { 86 int id_pfr1, ret; 87 88 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 89 90 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 91 debug("id_pfr1: 0x%08x\n", id_pfr1); 92 /* Generic Timer Extension available? */ 93 if ((id_pfr1 >> 16) & 0xf) { 94 debug("Setting CNTFRQ\n"); 95 /* CNTFRQ == 24 MHz */ 96 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); 97 } 98 99 ret = axp_gpio_init(); 100 if (ret) 101 return ret; 102 103 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 104 return soft_i2c_board_init(); 105 } 106 107 int dram_init(void) 108 { 109 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 110 111 return 0; 112 } 113 114 #ifdef CONFIG_GENERIC_MMC 115 static void mmc_pinmux_setup(int sdc) 116 { 117 unsigned int pin; 118 __maybe_unused int pins; 119 120 switch (sdc) { 121 case 0: 122 /* SDC0: PF0-PF5 */ 123 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 124 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 125 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 126 sunxi_gpio_set_drv(pin, 2); 127 } 128 break; 129 130 case 1: 131 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 132 133 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 134 if (pins == SUNXI_GPIO_H) { 135 /* SDC1: PH22-PH-27 */ 136 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 137 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 138 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 139 sunxi_gpio_set_drv(pin, 2); 140 } 141 } else { 142 /* SDC1: PG0-PG5 */ 143 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 144 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 145 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 146 sunxi_gpio_set_drv(pin, 2); 147 } 148 } 149 #elif defined(CONFIG_MACH_SUN5I) 150 /* SDC1: PG3-PG8 */ 151 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 152 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 153 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 154 sunxi_gpio_set_drv(pin, 2); 155 } 156 #elif defined(CONFIG_MACH_SUN6I) 157 /* SDC1: PG0-PG5 */ 158 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 159 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 160 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 161 sunxi_gpio_set_drv(pin, 2); 162 } 163 #elif defined(CONFIG_MACH_SUN8I) 164 if (pins == SUNXI_GPIO_D) { 165 /* SDC1: PD2-PD7 */ 166 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 167 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 168 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 169 sunxi_gpio_set_drv(pin, 2); 170 } 171 } else { 172 /* SDC1: PG0-PG5 */ 173 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 174 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 175 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 176 sunxi_gpio_set_drv(pin, 2); 177 } 178 } 179 #endif 180 break; 181 182 case 2: 183 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 184 185 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 186 /* SDC2: PC6-PC11 */ 187 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 188 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 189 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 190 sunxi_gpio_set_drv(pin, 2); 191 } 192 #elif defined(CONFIG_MACH_SUN5I) 193 if (pins == SUNXI_GPIO_E) { 194 /* SDC2: PE4-PE9 */ 195 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 196 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 197 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 198 sunxi_gpio_set_drv(pin, 2); 199 } 200 } else { 201 /* SDC2: PC6-PC15 */ 202 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 203 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 204 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 205 sunxi_gpio_set_drv(pin, 2); 206 } 207 } 208 #elif defined(CONFIG_MACH_SUN6I) 209 if (pins == SUNXI_GPIO_A) { 210 /* SDC2: PA9-PA14 */ 211 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 212 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 213 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 214 sunxi_gpio_set_drv(pin, 2); 215 } 216 } else { 217 /* SDC2: PC6-PC15, PC24 */ 218 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 219 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 220 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 221 sunxi_gpio_set_drv(pin, 2); 222 } 223 224 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 225 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 226 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 227 } 228 #elif defined(CONFIG_MACH_SUN8I) 229 /* SDC2: PC5-PC6, PC8-PC16 */ 230 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 231 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 232 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 233 sunxi_gpio_set_drv(pin, 2); 234 } 235 236 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 237 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 238 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 239 sunxi_gpio_set_drv(pin, 2); 240 } 241 #endif 242 break; 243 244 case 3: 245 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 246 247 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 248 /* SDC3: PI4-PI9 */ 249 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 250 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 251 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 252 sunxi_gpio_set_drv(pin, 2); 253 } 254 #elif defined(CONFIG_MACH_SUN6I) 255 if (pins == SUNXI_GPIO_A) { 256 /* SDC3: PA9-PA14 */ 257 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 258 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 259 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 260 sunxi_gpio_set_drv(pin, 2); 261 } 262 } else { 263 /* SDC3: PC6-PC15, PC24 */ 264 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 265 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 266 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 267 sunxi_gpio_set_drv(pin, 2); 268 } 269 270 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 271 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 272 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 273 } 274 #endif 275 break; 276 277 default: 278 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 279 break; 280 } 281 } 282 283 int board_mmc_init(bd_t *bis) 284 { 285 __maybe_unused struct mmc *mmc0, *mmc1; 286 __maybe_unused char buf[512]; 287 288 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 289 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 290 if (!mmc0) 291 return -1; 292 293 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 294 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 295 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 296 if (!mmc1) 297 return -1; 298 #endif 299 300 #if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 301 /* 302 * Both mmc0 and mmc2 are bootable, figure out where we're booting 303 * from. Try mmc0 first, just like the brom does. 304 */ 305 if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 && 306 mmc0->block_dev.block_read(0, 16, 1, buf) == 1) { 307 buf[12] = 0; 308 if (strcmp(&buf[4], "eGON.BT0") == 0) 309 return 0; 310 } 311 312 /* no bootable card in mmc0, so we must be booting from mmc2, swap */ 313 mmc0->block_dev.dev = 1; 314 mmc1->block_dev.dev = 0; 315 #endif 316 317 return 0; 318 } 319 #endif 320 321 #ifdef CONFIG_NAND 322 void board_nand_init(void) 323 { 324 unsigned int pin; 325 static u8 ports[] = CONFIG_NAND_SUNXI_GPC_PORTS; 326 327 /* Configure AHB muxes to connect output pins with NAND controller */ 328 for (pin = 0; pin < 16; pin++) 329 sunxi_gpio_set_cfgpin(SUNXI_GPC(pin), SUNXI_GPC_NAND); 330 331 for (pin = 0; pin < ARRAY_SIZE(ports); pin++) 332 sunxi_gpio_set_cfgpin(SUNXI_GPC(ports[pin]), SUNXI_GPC_NAND); 333 } 334 #endif 335 336 void i2c_init_board(void) 337 { 338 #ifdef CONFIG_I2C0_ENABLE 339 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) 340 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 341 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 342 clock_twi_onoff(0, 1); 343 #elif defined(CONFIG_MACH_SUN6I) 344 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 345 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 346 clock_twi_onoff(0, 1); 347 #elif defined(CONFIG_MACH_SUN8I) 348 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 349 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 350 clock_twi_onoff(0, 1); 351 #endif 352 #endif 353 354 #ifdef CONFIG_I2C1_ENABLE 355 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 356 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 357 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 358 clock_twi_onoff(1, 1); 359 #elif defined(CONFIG_MACH_SUN5I) 360 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 361 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 362 clock_twi_onoff(1, 1); 363 #elif defined(CONFIG_MACH_SUN6I) 364 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 365 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 366 clock_twi_onoff(1, 1); 367 #elif defined(CONFIG_MACH_SUN8I) 368 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 369 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 370 clock_twi_onoff(1, 1); 371 #endif 372 #endif 373 374 #ifdef CONFIG_I2C2_ENABLE 375 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 376 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 377 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 378 clock_twi_onoff(2, 1); 379 #elif defined(CONFIG_MACH_SUN5I) 380 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 381 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 382 clock_twi_onoff(2, 1); 383 #elif defined(CONFIG_MACH_SUN6I) 384 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 385 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 386 clock_twi_onoff(2, 1); 387 #elif defined(CONFIG_MACH_SUN8I) 388 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 389 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 390 clock_twi_onoff(2, 1); 391 #endif 392 #endif 393 394 #ifdef CONFIG_I2C3_ENABLE 395 #if defined(CONFIG_MACH_SUN6I) 396 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 397 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 398 clock_twi_onoff(3, 1); 399 #elif defined(CONFIG_MACH_SUN7I) 400 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 401 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 402 clock_twi_onoff(3, 1); 403 #endif 404 #endif 405 406 #ifdef CONFIG_I2C4_ENABLE 407 #if defined(CONFIG_MACH_SUN7I) 408 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 409 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 410 clock_twi_onoff(4, 1); 411 #endif 412 #endif 413 } 414 415 #ifdef CONFIG_SPL_BUILD 416 void sunxi_board_init(void) 417 { 418 int power_failed = 0; 419 unsigned long ramsize; 420 421 #ifdef CONFIG_AXP152_POWER 422 power_failed = axp152_init(); 423 power_failed |= axp152_set_dcdc2(1400); 424 power_failed |= axp152_set_dcdc3(1500); 425 power_failed |= axp152_set_dcdc4(1250); 426 power_failed |= axp152_set_ldo2(3000); 427 #endif 428 #ifdef CONFIG_AXP209_POWER 429 power_failed |= axp209_init(); 430 power_failed |= axp209_set_dcdc2(1400); 431 power_failed |= axp209_set_dcdc3(1250); 432 power_failed |= axp209_set_ldo2(3000); 433 power_failed |= axp209_set_ldo3(2800); 434 power_failed |= axp209_set_ldo4(2800); 435 #endif 436 #ifdef CONFIG_AXP221_POWER 437 power_failed = axp221_init(); 438 power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT); 439 power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */ 440 power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */ 441 #ifdef CONFIG_MACH_SUN6I 442 power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */ 443 #else 444 power_failed |= axp221_set_dcdc4(0); /* A23:unused */ 445 #endif 446 power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */ 447 power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); 448 power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); 449 power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); 450 power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); 451 power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); 452 power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT); 453 #endif 454 455 printf("DRAM:"); 456 ramsize = sunxi_dram_init(); 457 printf(" %lu MiB\n", ramsize >> 20); 458 if (!ramsize) 459 hang(); 460 461 /* 462 * Only clock up the CPU to full speed if we are reasonably 463 * assured it's being powered with suitable core voltage 464 */ 465 if (!power_failed) 466 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 467 else 468 printf("Failed to set core voltage! Can't set CPU frequency\n"); 469 } 470 #endif 471 472 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) 473 extern const struct musb_platform_ops sunxi_musb_ops; 474 475 static struct musb_hdrc_config musb_config = { 476 .multipoint = 1, 477 .dyn_fifo = 1, 478 .num_eps = 6, 479 .ram_bits = 11, 480 }; 481 482 static struct musb_hdrc_platform_data musb_plat = { 483 #if defined(CONFIG_MUSB_HOST) 484 .mode = MUSB_HOST, 485 #else 486 .mode = MUSB_PERIPHERAL, 487 #endif 488 .config = &musb_config, 489 .power = 250, 490 .platform_ops = &sunxi_musb_ops, 491 }; 492 #endif 493 494 #ifdef CONFIG_USB_GADGET 495 int g_dnl_board_usb_cable_connected(void) 496 { 497 return sunxi_usb_phy_vbus_detect(0); 498 } 499 #endif 500 501 #ifdef CONFIG_SERIAL_TAG 502 void get_board_serial(struct tag_serialnr *serialnr) 503 { 504 char *serial_string; 505 unsigned long long serial; 506 507 serial_string = getenv("serial#"); 508 509 if (serial_string) { 510 serial = simple_strtoull(serial_string, NULL, 16); 511 512 serialnr->high = (unsigned int) (serial >> 32); 513 serialnr->low = (unsigned int) (serial & 0xffffffff); 514 } else { 515 serialnr->high = 0; 516 serialnr->low = 0; 517 } 518 } 519 #endif 520 521 #ifdef CONFIG_MISC_INIT_R 522 int misc_init_r(void) 523 { 524 char serial_string[17] = { 0 }; 525 unsigned int sid[4]; 526 uint8_t mac_addr[6]; 527 int ret; 528 529 ret = sunxi_get_sid(sid); 530 if (ret == 0 && sid[0] != 0 && sid[3] != 0) { 531 if (!getenv("ethaddr")) { 532 /* Non OUI / registered MAC address */ 533 mac_addr[0] = 0x02; 534 mac_addr[1] = (sid[0] >> 0) & 0xff; 535 mac_addr[2] = (sid[3] >> 24) & 0xff; 536 mac_addr[3] = (sid[3] >> 16) & 0xff; 537 mac_addr[4] = (sid[3] >> 8) & 0xff; 538 mac_addr[5] = (sid[3] >> 0) & 0xff; 539 540 eth_setenv_enetaddr("ethaddr", mac_addr); 541 } 542 543 if (!getenv("serial#")) { 544 snprintf(serial_string, sizeof(serial_string), 545 "%08x%08x", sid[0], sid[3]); 546 547 setenv("serial#", serial_string); 548 } 549 } 550 551 #ifndef CONFIG_MACH_SUN9I 552 ret = sunxi_usb_phy_probe(); 553 if (ret) 554 return ret; 555 #endif 556 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) 557 musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE); 558 #endif 559 return 0; 560 } 561 #endif 562 563 #ifdef CONFIG_OF_BOARD_SETUP 564 int ft_board_setup(void *blob, bd_t *bd) 565 { 566 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 567 return sunxi_simplefb_setup(blob); 568 #endif 569 } 570 #endif /* CONFIG_OF_BOARD_SETUP */ 571