1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 5 * 6 * (C) Copyright 2007-2011 7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 8 * Tom Cubie <tangliang@allwinnertech.com> 9 * 10 * Some board init for the Allwinner A10-evb board. 11 */ 12 13 #include <common.h> 14 #include <dm.h> 15 #include <mmc.h> 16 #include <axp_pmic.h> 17 #include <generic-phy.h> 18 #include <phy-sun4i-usb.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/cpu.h> 21 #include <asm/arch/display.h> 22 #include <asm/arch/dram.h> 23 #include <asm/arch/gpio.h> 24 #include <asm/arch/mmc.h> 25 #include <asm/arch/spl.h> 26 #ifndef CONFIG_ARM64 27 #include <asm/armv7.h> 28 #endif 29 #include <asm/gpio.h> 30 #include <asm/io.h> 31 #include <crc.h> 32 #include <environment.h> 33 #include <linux/libfdt.h> 34 #include <nand.h> 35 #include <net.h> 36 #include <spl.h> 37 #include <sy8106a.h> 38 #include <asm/setup.h> 39 40 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 41 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 42 int soft_i2c_gpio_sda; 43 int soft_i2c_gpio_scl; 44 45 static int soft_i2c_board_init(void) 46 { 47 int ret; 48 49 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 50 if (soft_i2c_gpio_sda < 0) { 51 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 52 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 53 return soft_i2c_gpio_sda; 54 } 55 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 56 if (ret) { 57 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 58 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 59 return ret; 60 } 61 62 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 63 if (soft_i2c_gpio_scl < 0) { 64 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 65 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 66 return soft_i2c_gpio_scl; 67 } 68 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 69 if (ret) { 70 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 71 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 72 return ret; 73 } 74 75 return 0; 76 } 77 #else 78 static int soft_i2c_board_init(void) { return 0; } 79 #endif 80 81 DECLARE_GLOBAL_DATA_PTR; 82 83 void i2c_init_board(void) 84 { 85 #ifdef CONFIG_I2C0_ENABLE 86 #if defined(CONFIG_MACH_SUN4I) || \ 87 defined(CONFIG_MACH_SUN5I) || \ 88 defined(CONFIG_MACH_SUN7I) || \ 89 defined(CONFIG_MACH_SUN8I_R40) 90 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 91 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 92 clock_twi_onoff(0, 1); 93 #elif defined(CONFIG_MACH_SUN6I) 94 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 95 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 96 clock_twi_onoff(0, 1); 97 #elif defined(CONFIG_MACH_SUN8I) 98 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 99 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 100 clock_twi_onoff(0, 1); 101 #endif 102 #endif 103 104 #ifdef CONFIG_I2C1_ENABLE 105 #if defined(CONFIG_MACH_SUN4I) || \ 106 defined(CONFIG_MACH_SUN7I) || \ 107 defined(CONFIG_MACH_SUN8I_R40) 108 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 109 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 110 clock_twi_onoff(1, 1); 111 #elif defined(CONFIG_MACH_SUN5I) 112 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 113 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 114 clock_twi_onoff(1, 1); 115 #elif defined(CONFIG_MACH_SUN6I) 116 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 117 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 118 clock_twi_onoff(1, 1); 119 #elif defined(CONFIG_MACH_SUN8I) 120 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 121 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 122 clock_twi_onoff(1, 1); 123 #endif 124 #endif 125 126 #ifdef CONFIG_I2C2_ENABLE 127 #if defined(CONFIG_MACH_SUN4I) || \ 128 defined(CONFIG_MACH_SUN7I) || \ 129 defined(CONFIG_MACH_SUN8I_R40) 130 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 131 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 132 clock_twi_onoff(2, 1); 133 #elif defined(CONFIG_MACH_SUN5I) 134 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 135 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 136 clock_twi_onoff(2, 1); 137 #elif defined(CONFIG_MACH_SUN6I) 138 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 139 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 140 clock_twi_onoff(2, 1); 141 #elif defined(CONFIG_MACH_SUN8I) 142 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 143 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 144 clock_twi_onoff(2, 1); 145 #endif 146 #endif 147 148 #ifdef CONFIG_I2C3_ENABLE 149 #if defined(CONFIG_MACH_SUN6I) 150 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 151 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 152 clock_twi_onoff(3, 1); 153 #elif defined(CONFIG_MACH_SUN7I) || \ 154 defined(CONFIG_MACH_SUN8I_R40) 155 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 156 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 157 clock_twi_onoff(3, 1); 158 #endif 159 #endif 160 161 #ifdef CONFIG_I2C4_ENABLE 162 #if defined(CONFIG_MACH_SUN7I) || \ 163 defined(CONFIG_MACH_SUN8I_R40) 164 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 165 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 166 clock_twi_onoff(4, 1); 167 #endif 168 #endif 169 170 #ifdef CONFIG_R_I2C_ENABLE 171 clock_twi_onoff(5, 1); 172 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); 173 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); 174 #endif 175 } 176 177 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT) 178 enum env_location env_get_location(enum env_operation op, int prio) 179 { 180 switch (prio) { 181 case 0: 182 return ENVL_FAT; 183 184 case 1: 185 return ENVL_MMC; 186 187 default: 188 return ENVL_UNKNOWN; 189 } 190 } 191 #endif 192 193 /* add board specific code here */ 194 int board_init(void) 195 { 196 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin; 197 198 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 199 200 #ifndef CONFIG_ARM64 201 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 202 debug("id_pfr1: 0x%08x\n", id_pfr1); 203 /* Generic Timer Extension available? */ 204 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { 205 uint32_t freq; 206 207 debug("Setting CNTFRQ\n"); 208 209 /* 210 * CNTFRQ is a secure register, so we will crash if we try to 211 * write this from the non-secure world (read is OK, though). 212 * In case some bootcode has already set the correct value, 213 * we avoid the risk of writing to it. 214 */ 215 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); 216 if (freq != COUNTER_FREQUENCY) { 217 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", 218 freq, COUNTER_FREQUENCY); 219 #ifdef CONFIG_NON_SECURE 220 printf("arch timer frequency is wrong, but cannot adjust it\n"); 221 #else 222 asm volatile("mcr p15, 0, %0, c14, c0, 0" 223 : : "r"(COUNTER_FREQUENCY)); 224 #endif 225 } 226 } 227 #endif /* !CONFIG_ARM64 */ 228 229 ret = axp_gpio_init(); 230 if (ret) 231 return ret; 232 233 #ifdef CONFIG_SATAPWR 234 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR); 235 gpio_request(satapwr_pin, "satapwr"); 236 gpio_direction_output(satapwr_pin, 1); 237 /* Give attached sata device time to power-up to avoid link timeouts */ 238 mdelay(500); 239 #endif 240 #ifdef CONFIG_MACPWR 241 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR); 242 gpio_request(macpwr_pin, "macpwr"); 243 gpio_direction_output(macpwr_pin, 1); 244 #endif 245 246 #ifdef CONFIG_DM_I2C 247 /* 248 * Temporary workaround for enabling I2C clocks until proper sunxi DM 249 * clk, reset and pinctrl drivers land. 250 */ 251 i2c_init_board(); 252 #endif 253 254 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 255 return soft_i2c_board_init(); 256 } 257 258 int dram_init(void) 259 { 260 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 261 262 return 0; 263 } 264 265 #if defined(CONFIG_NAND_SUNXI) 266 static void nand_pinmux_setup(void) 267 { 268 unsigned int pin; 269 270 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) 271 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 272 273 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I 274 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) 275 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 276 #endif 277 /* sun4i / sun7i do have a PC23, but it is not used for nand, 278 * only sun7i has a PC24 */ 279 #ifdef CONFIG_MACH_SUN7I 280 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 281 #endif 282 } 283 284 static void nand_clock_setup(void) 285 { 286 struct sunxi_ccm_reg *const ccm = 287 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 288 289 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 290 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ 291 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I 292 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); 293 #endif 294 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 295 } 296 297 void board_nand_init(void) 298 { 299 nand_pinmux_setup(); 300 nand_clock_setup(); 301 #ifndef CONFIG_SPL_BUILD 302 sunxi_nand_init(); 303 #endif 304 } 305 #endif 306 307 #ifdef CONFIG_MMC 308 static void mmc_pinmux_setup(int sdc) 309 { 310 unsigned int pin; 311 __maybe_unused int pins; 312 313 switch (sdc) { 314 case 0: 315 /* SDC0: PF0-PF5 */ 316 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 317 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 318 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 319 sunxi_gpio_set_drv(pin, 2); 320 } 321 break; 322 323 case 1: 324 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 325 326 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ 327 defined(CONFIG_MACH_SUN8I_R40) 328 if (pins == SUNXI_GPIO_H) { 329 /* SDC1: PH22-PH-27 */ 330 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 331 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 332 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 333 sunxi_gpio_set_drv(pin, 2); 334 } 335 } else { 336 /* SDC1: PG0-PG5 */ 337 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 338 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 339 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 340 sunxi_gpio_set_drv(pin, 2); 341 } 342 } 343 #elif defined(CONFIG_MACH_SUN5I) 344 /* SDC1: PG3-PG8 */ 345 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 346 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 347 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 348 sunxi_gpio_set_drv(pin, 2); 349 } 350 #elif defined(CONFIG_MACH_SUN6I) 351 /* SDC1: PG0-PG5 */ 352 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 353 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 354 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 355 sunxi_gpio_set_drv(pin, 2); 356 } 357 #elif defined(CONFIG_MACH_SUN8I) 358 if (pins == SUNXI_GPIO_D) { 359 /* SDC1: PD2-PD7 */ 360 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 361 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 362 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 363 sunxi_gpio_set_drv(pin, 2); 364 } 365 } else { 366 /* SDC1: PG0-PG5 */ 367 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 368 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 369 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 370 sunxi_gpio_set_drv(pin, 2); 371 } 372 } 373 #endif 374 break; 375 376 case 2: 377 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 378 379 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 380 /* SDC2: PC6-PC11 */ 381 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 382 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 383 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 384 sunxi_gpio_set_drv(pin, 2); 385 } 386 #elif defined(CONFIG_MACH_SUN5I) 387 if (pins == SUNXI_GPIO_E) { 388 /* SDC2: PE4-PE9 */ 389 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 390 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 391 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 392 sunxi_gpio_set_drv(pin, 2); 393 } 394 } else { 395 /* SDC2: PC6-PC15 */ 396 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 397 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 398 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 399 sunxi_gpio_set_drv(pin, 2); 400 } 401 } 402 #elif defined(CONFIG_MACH_SUN6I) 403 if (pins == SUNXI_GPIO_A) { 404 /* SDC2: PA9-PA14 */ 405 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 406 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 407 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 408 sunxi_gpio_set_drv(pin, 2); 409 } 410 } else { 411 /* SDC2: PC6-PC15, PC24 */ 412 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 413 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 414 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 415 sunxi_gpio_set_drv(pin, 2); 416 } 417 418 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 419 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 420 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 421 } 422 #elif defined(CONFIG_MACH_SUN8I_R40) 423 /* SDC2: PC6-PC15, PC24 */ 424 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 425 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 426 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 427 sunxi_gpio_set_drv(pin, 2); 428 } 429 430 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 431 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 432 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 433 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) 434 /* SDC2: PC5-PC6, PC8-PC16 */ 435 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 436 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 437 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 438 sunxi_gpio_set_drv(pin, 2); 439 } 440 441 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 442 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 443 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 444 sunxi_gpio_set_drv(pin, 2); 445 } 446 #elif defined(CONFIG_MACH_SUN50I_H6) 447 /* SDC2: PC4-PC14 */ 448 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) { 449 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 450 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 451 sunxi_gpio_set_drv(pin, 2); 452 } 453 #elif defined(CONFIG_MACH_SUN9I) 454 /* SDC2: PC6-PC16 */ 455 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) { 456 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 457 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 458 sunxi_gpio_set_drv(pin, 2); 459 } 460 #endif 461 break; 462 463 case 3: 464 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 465 466 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ 467 defined(CONFIG_MACH_SUN8I_R40) 468 /* SDC3: PI4-PI9 */ 469 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 470 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 471 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 472 sunxi_gpio_set_drv(pin, 2); 473 } 474 #elif defined(CONFIG_MACH_SUN6I) 475 if (pins == SUNXI_GPIO_A) { 476 /* SDC3: PA9-PA14 */ 477 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 478 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 479 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 480 sunxi_gpio_set_drv(pin, 2); 481 } 482 } else { 483 /* SDC3: PC6-PC15, PC24 */ 484 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 485 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 486 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 487 sunxi_gpio_set_drv(pin, 2); 488 } 489 490 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 491 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 492 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 493 } 494 #endif 495 break; 496 497 default: 498 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 499 break; 500 } 501 } 502 503 int board_mmc_init(bd_t *bis) 504 { 505 __maybe_unused struct mmc *mmc0, *mmc1; 506 507 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 508 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 509 if (!mmc0) 510 return -1; 511 512 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 513 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 514 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 515 if (!mmc1) 516 return -1; 517 #endif 518 519 return 0; 520 } 521 #endif 522 523 #ifdef CONFIG_SPL_BUILD 524 void sunxi_board_init(void) 525 { 526 int power_failed = 0; 527 528 #ifdef CONFIG_SY8106A_POWER 529 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); 530 #endif 531 532 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 533 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 534 defined CONFIG_AXP818_POWER 535 power_failed = axp_init(); 536 537 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 538 defined CONFIG_AXP818_POWER 539 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); 540 #endif 541 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); 542 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); 543 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) 544 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); 545 #endif 546 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 547 defined CONFIG_AXP818_POWER 548 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); 549 #endif 550 551 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 552 defined CONFIG_AXP818_POWER 553 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); 554 #endif 555 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); 556 #if !defined(CONFIG_AXP152_POWER) 557 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); 558 #endif 559 #ifdef CONFIG_AXP209_POWER 560 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); 561 #endif 562 563 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ 564 defined(CONFIG_AXP818_POWER) 565 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); 566 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); 567 #if !defined CONFIG_AXP809_POWER 568 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); 569 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); 570 #endif 571 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); 572 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); 573 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); 574 #endif 575 576 #ifdef CONFIG_AXP818_POWER 577 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); 578 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); 579 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); 580 #endif 581 582 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 583 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); 584 #endif 585 #endif 586 printf("DRAM:"); 587 gd->ram_size = sunxi_dram_init(); 588 printf(" %d MiB\n", (int)(gd->ram_size >> 20)); 589 if (!gd->ram_size) 590 hang(); 591 592 /* 593 * Only clock up the CPU to full speed if we are reasonably 594 * assured it's being powered with suitable core voltage 595 */ 596 if (!power_failed) 597 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 598 else 599 printf("Failed to set core voltage! Can't set CPU frequency\n"); 600 } 601 #endif 602 603 #ifdef CONFIG_USB_GADGET 604 int g_dnl_board_usb_cable_connected(void) 605 { 606 struct udevice *dev; 607 struct phy phy; 608 int ret; 609 610 ret = uclass_get_device(UCLASS_USB_DEV_GENERIC, 0, &dev); 611 if (ret) { 612 pr_err("%s: Cannot find USB device\n", __func__); 613 return ret; 614 } 615 616 ret = generic_phy_get_by_name(dev, "usb", &phy); 617 if (ret) { 618 pr_err("failed to get %s USB PHY\n", dev->name); 619 return ret; 620 } 621 622 ret = generic_phy_init(&phy); 623 if (ret) { 624 pr_err("failed to init %s USB PHY\n", dev->name); 625 return ret; 626 } 627 628 ret = sun4i_usb_phy_vbus_detect(&phy); 629 if (ret == 1) { 630 pr_err("A charger is plugged into the OTG\n"); 631 return -ENODEV; 632 } 633 634 return ret; 635 } 636 #endif 637 638 #ifdef CONFIG_SERIAL_TAG 639 void get_board_serial(struct tag_serialnr *serialnr) 640 { 641 char *serial_string; 642 unsigned long long serial; 643 644 serial_string = env_get("serial#"); 645 646 if (serial_string) { 647 serial = simple_strtoull(serial_string, NULL, 16); 648 649 serialnr->high = (unsigned int) (serial >> 32); 650 serialnr->low = (unsigned int) (serial & 0xffffffff); 651 } else { 652 serialnr->high = 0; 653 serialnr->low = 0; 654 } 655 } 656 #endif 657 658 /* 659 * Check the SPL header for the "sunxi" variant. If found: parse values 660 * that might have been passed by the loader ("fel" utility), and update 661 * the environment accordingly. 662 */ 663 static void parse_spl_header(const uint32_t spl_addr) 664 { 665 struct boot_file_head *spl = (void *)(ulong)spl_addr; 666 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0) 667 return; /* signature mismatch, no usable header */ 668 669 uint8_t spl_header_version = spl->spl_signature[3]; 670 if (spl_header_version != SPL_HEADER_VERSION) { 671 printf("sunxi SPL version mismatch: expected %u, got %u\n", 672 SPL_HEADER_VERSION, spl_header_version); 673 return; 674 } 675 if (!spl->fel_script_address) 676 return; 677 678 if (spl->fel_uEnv_length != 0) { 679 /* 680 * data is expected in uEnv.txt compatible format, so "env 681 * import -t" the string(s) at fel_script_address right away. 682 */ 683 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address, 684 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL); 685 return; 686 } 687 /* otherwise assume .scr format (mkimage-type script) */ 688 env_set_hex("fel_scriptaddr", spl->fel_script_address); 689 } 690 691 /* 692 * Note this function gets called multiple times. 693 * It must not make any changes to env variables which already exist. 694 */ 695 static void setup_environment(const void *fdt) 696 { 697 char serial_string[17] = { 0 }; 698 unsigned int sid[4]; 699 uint8_t mac_addr[6]; 700 char ethaddr[16]; 701 int i, ret; 702 703 ret = sunxi_get_sid(sid); 704 if (ret == 0 && sid[0] != 0) { 705 /* 706 * The single words 1 - 3 of the SID have quite a few bits 707 * which are the same on many models, so we take a crc32 708 * of all 3 words, to get a more unique value. 709 * 710 * Note we only do this on newer SoCs as we cannot change 711 * the algorithm on older SoCs since those have been using 712 * fixed mac-addresses based on only using word 3 for a 713 * long time and changing a fixed mac-address with an 714 * u-boot update is not good. 715 */ 716 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ 717 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ 718 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) 719 sid[3] = crc32(0, (unsigned char *)&sid[1], 12); 720 #endif 721 722 /* Ensure the NIC specific bytes of the mac are not all 0 */ 723 if ((sid[3] & 0xffffff) == 0) 724 sid[3] |= 0x800000; 725 726 for (i = 0; i < 4; i++) { 727 sprintf(ethaddr, "ethernet%d", i); 728 if (!fdt_get_alias(fdt, ethaddr)) 729 continue; 730 731 if (i == 0) 732 strcpy(ethaddr, "ethaddr"); 733 else 734 sprintf(ethaddr, "eth%daddr", i); 735 736 if (env_get(ethaddr)) 737 continue; 738 739 /* Non OUI / registered MAC address */ 740 mac_addr[0] = (i << 4) | 0x02; 741 mac_addr[1] = (sid[0] >> 0) & 0xff; 742 mac_addr[2] = (sid[3] >> 24) & 0xff; 743 mac_addr[3] = (sid[3] >> 16) & 0xff; 744 mac_addr[4] = (sid[3] >> 8) & 0xff; 745 mac_addr[5] = (sid[3] >> 0) & 0xff; 746 747 eth_env_set_enetaddr(ethaddr, mac_addr); 748 } 749 750 if (!env_get("serial#")) { 751 snprintf(serial_string, sizeof(serial_string), 752 "%08x%08x", sid[0], sid[3]); 753 754 env_set("serial#", serial_string); 755 } 756 } 757 } 758 759 int misc_init_r(void) 760 { 761 uint boot; 762 763 env_set("fel_booted", NULL); 764 env_set("fel_scriptaddr", NULL); 765 env_set("mmc_bootdev", NULL); 766 767 boot = sunxi_get_boot_device(); 768 /* determine if we are running in FEL mode */ 769 if (boot == BOOT_DEVICE_BOARD) { 770 env_set("fel_booted", "1"); 771 parse_spl_header(SPL_ADDR); 772 /* or if we booted from MMC, and which one */ 773 } else if (boot == BOOT_DEVICE_MMC1) { 774 env_set("mmc_bootdev", "0"); 775 } else if (boot == BOOT_DEVICE_MMC2) { 776 env_set("mmc_bootdev", "1"); 777 } 778 779 setup_environment(gd->fdt_blob); 780 781 #ifdef CONFIG_USB_ETHER 782 usb_ether_init(); 783 #endif 784 785 return 0; 786 } 787 788 int ft_board_setup(void *blob, bd_t *bd) 789 { 790 int __maybe_unused r; 791 792 /* 793 * Call setup_environment again in case the boot fdt has 794 * ethernet aliases the u-boot copy does not have. 795 */ 796 setup_environment(blob); 797 798 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 799 r = sunxi_simplefb_setup(blob); 800 if (r) 801 return r; 802 #endif 803 return 0; 804 } 805 806 #ifdef CONFIG_SPL_LOAD_FIT 807 int board_fit_config_name_match(const char *name) 808 { 809 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR; 810 const char *cmp_str = (void *)(ulong)SPL_ADDR; 811 812 /* Check if there is a DT name stored in the SPL header and use that. */ 813 if (spl->dt_name_offset) { 814 cmp_str += spl->dt_name_offset; 815 } else { 816 #ifdef CONFIG_DEFAULT_DEVICE_TREE 817 cmp_str = CONFIG_DEFAULT_DEVICE_TREE; 818 #else 819 return 0; 820 #endif 821 }; 822 823 /* Differentiate the two Pine64 board DTs by their DRAM size. */ 824 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) { 825 if ((gd->ram_size > 512 * 1024 * 1024)) 826 return !strstr(name, "plus"); 827 else 828 return !!strstr(name, "plus"); 829 } else { 830 return strcmp(name, cmp_str); 831 } 832 } 833 #endif 834