1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #ifdef CONFIG_AXP152_POWER 17 #include <axp152.h> 18 #endif 19 #ifdef CONFIG_AXP209_POWER 20 #include <axp209.h> 21 #endif 22 #ifdef CONFIG_AXP221_POWER 23 #include <axp221.h> 24 #endif 25 #include <asm/arch/clock.h> 26 #include <asm/arch/cpu.h> 27 #include <asm/arch/display.h> 28 #include <asm/arch/dram.h> 29 #include <asm/arch/gpio.h> 30 #include <asm/arch/mmc.h> 31 #include <asm/arch/usb_phy.h> 32 #include <asm/gpio.h> 33 #include <asm/io.h> 34 #include <net.h> 35 36 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 37 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 38 int soft_i2c_gpio_sda; 39 int soft_i2c_gpio_scl; 40 41 static int soft_i2c_board_init(void) 42 { 43 int ret; 44 45 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 46 if (soft_i2c_gpio_sda < 0) { 47 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 48 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 49 return soft_i2c_gpio_sda; 50 } 51 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 52 if (ret) { 53 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 54 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 55 return ret; 56 } 57 58 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 59 if (soft_i2c_gpio_scl < 0) { 60 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 61 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 62 return soft_i2c_gpio_scl; 63 } 64 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 65 if (ret) { 66 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 67 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 68 return ret; 69 } 70 71 return 0; 72 } 73 #else 74 static int soft_i2c_board_init(void) { return 0; } 75 #endif 76 77 DECLARE_GLOBAL_DATA_PTR; 78 79 /* add board specific code here */ 80 int board_init(void) 81 { 82 int id_pfr1, ret; 83 84 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 85 86 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 87 debug("id_pfr1: 0x%08x\n", id_pfr1); 88 /* Generic Timer Extension available? */ 89 if ((id_pfr1 >> 16) & 0xf) { 90 debug("Setting CNTFRQ\n"); 91 /* CNTFRQ == 24 MHz */ 92 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); 93 } 94 95 ret = axp_gpio_init(); 96 if (ret) 97 return ret; 98 99 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 100 return soft_i2c_board_init(); 101 } 102 103 int dram_init(void) 104 { 105 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 106 107 return 0; 108 } 109 110 #if defined(CONFIG_SPL_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) 111 static void nand_pinmux_setup(void) 112 { 113 unsigned int pin; 114 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++) 115 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 116 117 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++) 118 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 119 120 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 121 } 122 123 static void nand_clock_setup(void) 124 { 125 struct sunxi_ccm_reg *const ccm = 126 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 127 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 128 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 129 } 130 #endif 131 132 #ifdef CONFIG_GENERIC_MMC 133 static void mmc_pinmux_setup(int sdc) 134 { 135 unsigned int pin; 136 __maybe_unused int pins; 137 138 switch (sdc) { 139 case 0: 140 /* SDC0: PF0-PF5 */ 141 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 142 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 143 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 144 sunxi_gpio_set_drv(pin, 2); 145 } 146 break; 147 148 case 1: 149 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 150 151 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 152 if (pins == SUNXI_GPIO_H) { 153 /* SDC1: PH22-PH-27 */ 154 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 155 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 156 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 157 sunxi_gpio_set_drv(pin, 2); 158 } 159 } else { 160 /* SDC1: PG0-PG5 */ 161 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 162 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 163 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 164 sunxi_gpio_set_drv(pin, 2); 165 } 166 } 167 #elif defined(CONFIG_MACH_SUN5I) 168 /* SDC1: PG3-PG8 */ 169 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 170 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 171 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 172 sunxi_gpio_set_drv(pin, 2); 173 } 174 #elif defined(CONFIG_MACH_SUN6I) 175 /* SDC1: PG0-PG5 */ 176 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 177 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 178 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 179 sunxi_gpio_set_drv(pin, 2); 180 } 181 #elif defined(CONFIG_MACH_SUN8I) 182 if (pins == SUNXI_GPIO_D) { 183 /* SDC1: PD2-PD7 */ 184 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 185 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 186 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 187 sunxi_gpio_set_drv(pin, 2); 188 } 189 } else { 190 /* SDC1: PG0-PG5 */ 191 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 192 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 193 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 194 sunxi_gpio_set_drv(pin, 2); 195 } 196 } 197 #endif 198 break; 199 200 case 2: 201 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 202 203 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 204 /* SDC2: PC6-PC11 */ 205 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 206 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 207 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 208 sunxi_gpio_set_drv(pin, 2); 209 } 210 #elif defined(CONFIG_MACH_SUN5I) 211 if (pins == SUNXI_GPIO_E) { 212 /* SDC2: PE4-PE9 */ 213 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 214 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 215 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 216 sunxi_gpio_set_drv(pin, 2); 217 } 218 } else { 219 /* SDC2: PC6-PC15 */ 220 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 221 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 222 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 223 sunxi_gpio_set_drv(pin, 2); 224 } 225 } 226 #elif defined(CONFIG_MACH_SUN6I) 227 if (pins == SUNXI_GPIO_A) { 228 /* SDC2: PA9-PA14 */ 229 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 230 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 231 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 232 sunxi_gpio_set_drv(pin, 2); 233 } 234 } else { 235 /* SDC2: PC6-PC15, PC24 */ 236 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 237 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 238 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 239 sunxi_gpio_set_drv(pin, 2); 240 } 241 242 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 243 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 244 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 245 } 246 #elif defined(CONFIG_MACH_SUN8I) 247 /* SDC2: PC5-PC6, PC8-PC16 */ 248 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 249 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 250 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 251 sunxi_gpio_set_drv(pin, 2); 252 } 253 254 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 255 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 256 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 257 sunxi_gpio_set_drv(pin, 2); 258 } 259 #endif 260 break; 261 262 case 3: 263 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 264 265 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 266 /* SDC3: PI4-PI9 */ 267 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 268 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 269 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 270 sunxi_gpio_set_drv(pin, 2); 271 } 272 #elif defined(CONFIG_MACH_SUN6I) 273 if (pins == SUNXI_GPIO_A) { 274 /* SDC3: PA9-PA14 */ 275 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 276 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 277 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 278 sunxi_gpio_set_drv(pin, 2); 279 } 280 } else { 281 /* SDC3: PC6-PC15, PC24 */ 282 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 283 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 284 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 285 sunxi_gpio_set_drv(pin, 2); 286 } 287 288 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 289 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 290 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 291 } 292 #endif 293 break; 294 295 default: 296 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 297 break; 298 } 299 } 300 301 int board_mmc_init(bd_t *bis) 302 { 303 __maybe_unused struct mmc *mmc0, *mmc1; 304 __maybe_unused char buf[512]; 305 306 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 307 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 308 if (!mmc0) 309 return -1; 310 311 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 312 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 313 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 314 if (!mmc1) 315 return -1; 316 #endif 317 318 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 319 /* 320 * On systems with an emmc (mmc2), figure out if we are booting from 321 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. 322 * are searched there first. Note we only do this for u-boot proper, 323 * not for the SPL, see spl_boot_device(). 324 */ 325 if (!sunxi_mmc_has_egon_boot_signature(mmc0) && 326 sunxi_mmc_has_egon_boot_signature(mmc1)) { 327 /* Booting from emmc / mmc2, swap */ 328 mmc0->block_dev.dev = 1; 329 mmc1->block_dev.dev = 0; 330 } 331 #endif 332 333 return 0; 334 } 335 #endif 336 337 void i2c_init_board(void) 338 { 339 #ifdef CONFIG_I2C0_ENABLE 340 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) 341 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 342 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 343 clock_twi_onoff(0, 1); 344 #elif defined(CONFIG_MACH_SUN6I) 345 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 346 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 347 clock_twi_onoff(0, 1); 348 #elif defined(CONFIG_MACH_SUN8I) 349 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 350 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 351 clock_twi_onoff(0, 1); 352 #endif 353 #endif 354 355 #ifdef CONFIG_I2C1_ENABLE 356 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 357 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 358 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 359 clock_twi_onoff(1, 1); 360 #elif defined(CONFIG_MACH_SUN5I) 361 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 362 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 363 clock_twi_onoff(1, 1); 364 #elif defined(CONFIG_MACH_SUN6I) 365 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 366 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 367 clock_twi_onoff(1, 1); 368 #elif defined(CONFIG_MACH_SUN8I) 369 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 370 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 371 clock_twi_onoff(1, 1); 372 #endif 373 #endif 374 375 #ifdef CONFIG_I2C2_ENABLE 376 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 377 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 378 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 379 clock_twi_onoff(2, 1); 380 #elif defined(CONFIG_MACH_SUN5I) 381 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 382 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 383 clock_twi_onoff(2, 1); 384 #elif defined(CONFIG_MACH_SUN6I) 385 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 386 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 387 clock_twi_onoff(2, 1); 388 #elif defined(CONFIG_MACH_SUN8I) 389 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 390 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 391 clock_twi_onoff(2, 1); 392 #endif 393 #endif 394 395 #ifdef CONFIG_I2C3_ENABLE 396 #if defined(CONFIG_MACH_SUN6I) 397 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 398 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 399 clock_twi_onoff(3, 1); 400 #elif defined(CONFIG_MACH_SUN7I) 401 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 402 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 403 clock_twi_onoff(3, 1); 404 #endif 405 #endif 406 407 #ifdef CONFIG_I2C4_ENABLE 408 #if defined(CONFIG_MACH_SUN7I) 409 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 410 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 411 clock_twi_onoff(4, 1); 412 #endif 413 #endif 414 } 415 416 #ifdef CONFIG_SPL_BUILD 417 void sunxi_board_init(void) 418 { 419 int power_failed = 0; 420 unsigned long ramsize; 421 422 #ifdef CONFIG_AXP152_POWER 423 power_failed = axp152_init(); 424 power_failed |= axp152_set_dcdc2(1400); 425 power_failed |= axp152_set_dcdc3(1500); 426 power_failed |= axp152_set_dcdc4(1250); 427 power_failed |= axp152_set_ldo2(3000); 428 #endif 429 #ifdef CONFIG_AXP209_POWER 430 power_failed |= axp209_init(); 431 power_failed |= axp209_set_dcdc2(1400); 432 power_failed |= axp209_set_dcdc3(1250); 433 power_failed |= axp209_set_ldo2(3000); 434 power_failed |= axp209_set_ldo3(2800); 435 power_failed |= axp209_set_ldo4(2800); 436 #endif 437 #ifdef CONFIG_AXP221_POWER 438 power_failed = axp221_init(); 439 power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT); 440 power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */ 441 power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */ 442 #ifdef CONFIG_MACH_SUN6I 443 power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */ 444 #else 445 power_failed |= axp221_set_dcdc4(0); /* A23:unused */ 446 #endif 447 power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */ 448 power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); 449 power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); 450 power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); 451 power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); 452 power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); 453 power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT); 454 #endif 455 456 #ifdef CONFIG_SPL_NAND_SUNXI 457 nand_pinmux_setup(); 458 nand_clock_setup(); 459 #endif 460 461 printf("DRAM:"); 462 ramsize = sunxi_dram_init(); 463 printf(" %lu MiB\n", ramsize >> 20); 464 if (!ramsize) 465 hang(); 466 467 /* 468 * Only clock up the CPU to full speed if we are reasonably 469 * assured it's being powered with suitable core voltage 470 */ 471 if (!power_failed) 472 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 473 else 474 printf("Failed to set core voltage! Can't set CPU frequency\n"); 475 } 476 #endif 477 478 #ifdef CONFIG_USB_GADGET 479 int g_dnl_board_usb_cable_connected(void) 480 { 481 return sunxi_usb_phy_vbus_detect(0); 482 } 483 #endif 484 485 #ifdef CONFIG_SERIAL_TAG 486 void get_board_serial(struct tag_serialnr *serialnr) 487 { 488 char *serial_string; 489 unsigned long long serial; 490 491 serial_string = getenv("serial#"); 492 493 if (serial_string) { 494 serial = simple_strtoull(serial_string, NULL, 16); 495 496 serialnr->high = (unsigned int) (serial >> 32); 497 serialnr->low = (unsigned int) (serial & 0xffffffff); 498 } else { 499 serialnr->high = 0; 500 serialnr->low = 0; 501 } 502 } 503 #endif 504 505 #ifdef CONFIG_MISC_INIT_R 506 int misc_init_r(void) 507 { 508 char serial_string[17] = { 0 }; 509 unsigned int sid[4]; 510 uint8_t mac_addr[6]; 511 int ret; 512 513 ret = sunxi_get_sid(sid); 514 if (ret == 0 && sid[0] != 0 && sid[3] != 0) { 515 if (!getenv("ethaddr")) { 516 /* Non OUI / registered MAC address */ 517 mac_addr[0] = 0x02; 518 mac_addr[1] = (sid[0] >> 0) & 0xff; 519 mac_addr[2] = (sid[3] >> 24) & 0xff; 520 mac_addr[3] = (sid[3] >> 16) & 0xff; 521 mac_addr[4] = (sid[3] >> 8) & 0xff; 522 mac_addr[5] = (sid[3] >> 0) & 0xff; 523 524 eth_setenv_enetaddr("ethaddr", mac_addr); 525 } 526 527 if (!getenv("serial#")) { 528 snprintf(serial_string, sizeof(serial_string), 529 "%08x%08x", sid[0], sid[3]); 530 531 setenv("serial#", serial_string); 532 } 533 } 534 535 #ifndef CONFIG_MACH_SUN9I 536 ret = sunxi_usb_phy_probe(); 537 if (ret) 538 return ret; 539 #endif 540 sunxi_musb_board_init(); 541 542 return 0; 543 } 544 #endif 545 546 #ifdef CONFIG_OF_BOARD_SETUP 547 int ft_board_setup(void *blob, bd_t *bd) 548 { 549 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 550 return sunxi_simplefb_setup(blob); 551 #endif 552 } 553 #endif /* CONFIG_OF_BOARD_SETUP */ 554