1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 5 * 6 * (C) Copyright 2007-2011 7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 8 * Tom Cubie <tangliang@allwinnertech.com> 9 * 10 * Some board init for the Allwinner A10-evb board. 11 */ 12 13 #include <common.h> 14 #include <dm.h> 15 #include <mmc.h> 16 #include <axp_pmic.h> 17 #include <generic-phy.h> 18 #include <phy-sun4i-usb.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/cpu.h> 21 #include <asm/arch/display.h> 22 #include <asm/arch/dram.h> 23 #include <asm/arch/gpio.h> 24 #include <asm/arch/mmc.h> 25 #include <asm/arch/spl.h> 26 #ifndef CONFIG_ARM64 27 #include <asm/armv7.h> 28 #endif 29 #include <asm/gpio.h> 30 #include <asm/io.h> 31 #include <u-boot/crc.h> 32 #include <environment.h> 33 #include <linux/libfdt.h> 34 #include <nand.h> 35 #include <net.h> 36 #include <spl.h> 37 #include <sy8106a.h> 38 #include <asm/setup.h> 39 40 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 41 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 42 int soft_i2c_gpio_sda; 43 int soft_i2c_gpio_scl; 44 45 static int soft_i2c_board_init(void) 46 { 47 int ret; 48 49 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 50 if (soft_i2c_gpio_sda < 0) { 51 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 52 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 53 return soft_i2c_gpio_sda; 54 } 55 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 56 if (ret) { 57 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 58 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 59 return ret; 60 } 61 62 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 63 if (soft_i2c_gpio_scl < 0) { 64 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 65 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 66 return soft_i2c_gpio_scl; 67 } 68 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 69 if (ret) { 70 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 71 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 72 return ret; 73 } 74 75 return 0; 76 } 77 #else 78 static int soft_i2c_board_init(void) { return 0; } 79 #endif 80 81 DECLARE_GLOBAL_DATA_PTR; 82 83 void i2c_init_board(void) 84 { 85 #ifdef CONFIG_I2C0_ENABLE 86 #if defined(CONFIG_MACH_SUN4I) || \ 87 defined(CONFIG_MACH_SUN5I) || \ 88 defined(CONFIG_MACH_SUN7I) || \ 89 defined(CONFIG_MACH_SUN8I_R40) 90 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 91 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 92 clock_twi_onoff(0, 1); 93 #elif defined(CONFIG_MACH_SUN6I) 94 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 95 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 96 clock_twi_onoff(0, 1); 97 #elif defined(CONFIG_MACH_SUN8I) 98 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 99 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 100 clock_twi_onoff(0, 1); 101 #elif defined(CONFIG_MACH_SUN50I) 102 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0); 103 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0); 104 clock_twi_onoff(0, 1); 105 #endif 106 #endif 107 108 #ifdef CONFIG_I2C1_ENABLE 109 #if defined(CONFIG_MACH_SUN4I) || \ 110 defined(CONFIG_MACH_SUN7I) || \ 111 defined(CONFIG_MACH_SUN8I_R40) 112 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 113 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 114 clock_twi_onoff(1, 1); 115 #elif defined(CONFIG_MACH_SUN5I) 116 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 117 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 118 clock_twi_onoff(1, 1); 119 #elif defined(CONFIG_MACH_SUN6I) 120 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 121 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 122 clock_twi_onoff(1, 1); 123 #elif defined(CONFIG_MACH_SUN8I) 124 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 125 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 126 clock_twi_onoff(1, 1); 127 #elif defined(CONFIG_MACH_SUN50I) 128 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1); 129 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1); 130 clock_twi_onoff(1, 1); 131 #endif 132 #endif 133 134 #ifdef CONFIG_I2C2_ENABLE 135 #if defined(CONFIG_MACH_SUN4I) || \ 136 defined(CONFIG_MACH_SUN7I) || \ 137 defined(CONFIG_MACH_SUN8I_R40) 138 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 139 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 140 clock_twi_onoff(2, 1); 141 #elif defined(CONFIG_MACH_SUN5I) 142 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 143 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 144 clock_twi_onoff(2, 1); 145 #elif defined(CONFIG_MACH_SUN6I) 146 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 147 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 148 clock_twi_onoff(2, 1); 149 #elif defined(CONFIG_MACH_SUN8I) 150 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 151 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 152 clock_twi_onoff(2, 1); 153 #elif defined(CONFIG_MACH_SUN50I) 154 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2); 155 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2); 156 clock_twi_onoff(2, 1); 157 #endif 158 #endif 159 160 #ifdef CONFIG_I2C3_ENABLE 161 #if defined(CONFIG_MACH_SUN6I) 162 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 163 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 164 clock_twi_onoff(3, 1); 165 #elif defined(CONFIG_MACH_SUN7I) || \ 166 defined(CONFIG_MACH_SUN8I_R40) 167 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 168 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 169 clock_twi_onoff(3, 1); 170 #endif 171 #endif 172 173 #ifdef CONFIG_I2C4_ENABLE 174 #if defined(CONFIG_MACH_SUN7I) || \ 175 defined(CONFIG_MACH_SUN8I_R40) 176 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 177 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 178 clock_twi_onoff(4, 1); 179 #endif 180 #endif 181 182 #ifdef CONFIG_R_I2C_ENABLE 183 #ifdef CONFIG_MACH_SUN50I 184 clock_twi_onoff(5, 1); 185 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI); 186 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI); 187 #else 188 clock_twi_onoff(5, 1); 189 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); 190 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); 191 #endif 192 #endif 193 } 194 195 #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT) 196 enum env_location env_get_location(enum env_operation op, int prio) 197 { 198 switch (prio) { 199 case 0: 200 return ENVL_FAT; 201 202 case 1: 203 return ENVL_MMC; 204 205 default: 206 return ENVL_UNKNOWN; 207 } 208 } 209 #endif 210 211 /* add board specific code here */ 212 int board_init(void) 213 { 214 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin; 215 216 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 217 218 #ifndef CONFIG_ARM64 219 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 220 debug("id_pfr1: 0x%08x\n", id_pfr1); 221 /* Generic Timer Extension available? */ 222 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { 223 uint32_t freq; 224 225 debug("Setting CNTFRQ\n"); 226 227 /* 228 * CNTFRQ is a secure register, so we will crash if we try to 229 * write this from the non-secure world (read is OK, though). 230 * In case some bootcode has already set the correct value, 231 * we avoid the risk of writing to it. 232 */ 233 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); 234 if (freq != COUNTER_FREQUENCY) { 235 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", 236 freq, COUNTER_FREQUENCY); 237 #ifdef CONFIG_NON_SECURE 238 printf("arch timer frequency is wrong, but cannot adjust it\n"); 239 #else 240 asm volatile("mcr p15, 0, %0, c14, c0, 0" 241 : : "r"(COUNTER_FREQUENCY)); 242 #endif 243 } 244 } 245 #endif /* !CONFIG_ARM64 */ 246 247 ret = axp_gpio_init(); 248 if (ret) 249 return ret; 250 251 #ifdef CONFIG_SATAPWR 252 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR); 253 gpio_request(satapwr_pin, "satapwr"); 254 gpio_direction_output(satapwr_pin, 1); 255 /* Give attached sata device time to power-up to avoid link timeouts */ 256 mdelay(500); 257 #endif 258 #ifdef CONFIG_MACPWR 259 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR); 260 gpio_request(macpwr_pin, "macpwr"); 261 gpio_direction_output(macpwr_pin, 1); 262 #endif 263 264 #ifdef CONFIG_DM_I2C 265 /* 266 * Temporary workaround for enabling I2C clocks until proper sunxi DM 267 * clk, reset and pinctrl drivers land. 268 */ 269 i2c_init_board(); 270 #endif 271 272 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 273 return soft_i2c_board_init(); 274 } 275 276 /* 277 * On older SoCs the SPL is actually at address zero, so using NULL as 278 * an error value does not work. 279 */ 280 #define INVALID_SPL_HEADER ((void *)~0UL) 281 282 static struct boot_file_head * get_spl_header(uint8_t req_version) 283 { 284 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR; 285 uint8_t spl_header_version = spl->spl_signature[3]; 286 287 /* Is there really the SPL header (still) there? */ 288 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0) 289 return INVALID_SPL_HEADER; 290 291 if (spl_header_version < req_version) { 292 printf("sunxi SPL version mismatch: expected %u, got %u\n", 293 req_version, spl_header_version); 294 return INVALID_SPL_HEADER; 295 } 296 297 return spl; 298 } 299 300 int dram_init(void) 301 { 302 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION); 303 304 if (spl == INVALID_SPL_HEADER) 305 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, 306 PHYS_SDRAM_0_SIZE); 307 else 308 gd->ram_size = (phys_addr_t)spl->dram_size << 20; 309 310 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE) 311 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE; 312 313 return 0; 314 } 315 316 #if defined(CONFIG_NAND_SUNXI) 317 static void nand_pinmux_setup(void) 318 { 319 unsigned int pin; 320 321 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) 322 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 323 324 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I 325 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) 326 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 327 #endif 328 /* sun4i / sun7i do have a PC23, but it is not used for nand, 329 * only sun7i has a PC24 */ 330 #ifdef CONFIG_MACH_SUN7I 331 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 332 #endif 333 } 334 335 static void nand_clock_setup(void) 336 { 337 struct sunxi_ccm_reg *const ccm = 338 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 339 340 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 341 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \ 342 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I 343 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0)); 344 #endif 345 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 346 } 347 348 void board_nand_init(void) 349 { 350 nand_pinmux_setup(); 351 nand_clock_setup(); 352 #ifndef CONFIG_SPL_BUILD 353 sunxi_nand_init(); 354 #endif 355 } 356 #endif 357 358 #ifdef CONFIG_MMC 359 static void mmc_pinmux_setup(int sdc) 360 { 361 unsigned int pin; 362 __maybe_unused int pins; 363 364 switch (sdc) { 365 case 0: 366 /* SDC0: PF0-PF5 */ 367 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 368 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 369 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 370 sunxi_gpio_set_drv(pin, 2); 371 } 372 break; 373 374 case 1: 375 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 376 377 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ 378 defined(CONFIG_MACH_SUN8I_R40) 379 if (pins == SUNXI_GPIO_H) { 380 /* SDC1: PH22-PH-27 */ 381 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 382 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 383 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 384 sunxi_gpio_set_drv(pin, 2); 385 } 386 } else { 387 /* SDC1: PG0-PG5 */ 388 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 389 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 390 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 391 sunxi_gpio_set_drv(pin, 2); 392 } 393 } 394 #elif defined(CONFIG_MACH_SUN5I) 395 /* SDC1: PG3-PG8 */ 396 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 397 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 398 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 399 sunxi_gpio_set_drv(pin, 2); 400 } 401 #elif defined(CONFIG_MACH_SUN6I) 402 /* SDC1: PG0-PG5 */ 403 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 404 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 405 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 406 sunxi_gpio_set_drv(pin, 2); 407 } 408 #elif defined(CONFIG_MACH_SUN8I) 409 if (pins == SUNXI_GPIO_D) { 410 /* SDC1: PD2-PD7 */ 411 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 412 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 413 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 414 sunxi_gpio_set_drv(pin, 2); 415 } 416 } else { 417 /* SDC1: PG0-PG5 */ 418 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 419 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 420 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 421 sunxi_gpio_set_drv(pin, 2); 422 } 423 } 424 #endif 425 break; 426 427 case 2: 428 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 429 430 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 431 /* SDC2: PC6-PC11 */ 432 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 433 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 434 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 435 sunxi_gpio_set_drv(pin, 2); 436 } 437 #elif defined(CONFIG_MACH_SUN5I) 438 if (pins == SUNXI_GPIO_E) { 439 /* SDC2: PE4-PE9 */ 440 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 441 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 442 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 443 sunxi_gpio_set_drv(pin, 2); 444 } 445 } else { 446 /* SDC2: PC6-PC15 */ 447 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 448 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 449 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 450 sunxi_gpio_set_drv(pin, 2); 451 } 452 } 453 #elif defined(CONFIG_MACH_SUN6I) 454 if (pins == SUNXI_GPIO_A) { 455 /* SDC2: PA9-PA14 */ 456 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 457 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 458 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 459 sunxi_gpio_set_drv(pin, 2); 460 } 461 } else { 462 /* SDC2: PC6-PC15, PC24 */ 463 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 464 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 465 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 466 sunxi_gpio_set_drv(pin, 2); 467 } 468 469 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 470 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 471 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 472 } 473 #elif defined(CONFIG_MACH_SUN8I_R40) 474 /* SDC2: PC6-PC15, PC24 */ 475 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 476 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 477 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 478 sunxi_gpio_set_drv(pin, 2); 479 } 480 481 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 482 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 483 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 484 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) 485 /* SDC2: PC5-PC6, PC8-PC16 */ 486 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 487 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 488 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 489 sunxi_gpio_set_drv(pin, 2); 490 } 491 492 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 493 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 494 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 495 sunxi_gpio_set_drv(pin, 2); 496 } 497 #elif defined(CONFIG_MACH_SUN50I_H6) 498 /* SDC2: PC4-PC14 */ 499 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) { 500 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 501 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 502 sunxi_gpio_set_drv(pin, 2); 503 } 504 #elif defined(CONFIG_MACH_SUN9I) 505 /* SDC2: PC6-PC16 */ 506 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) { 507 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 508 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 509 sunxi_gpio_set_drv(pin, 2); 510 } 511 #endif 512 break; 513 514 case 3: 515 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 516 517 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ 518 defined(CONFIG_MACH_SUN8I_R40) 519 /* SDC3: PI4-PI9 */ 520 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 521 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 522 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 523 sunxi_gpio_set_drv(pin, 2); 524 } 525 #elif defined(CONFIG_MACH_SUN6I) 526 if (pins == SUNXI_GPIO_A) { 527 /* SDC3: PA9-PA14 */ 528 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 529 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 530 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 531 sunxi_gpio_set_drv(pin, 2); 532 } 533 } else { 534 /* SDC3: PC6-PC15, PC24 */ 535 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 536 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 537 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 538 sunxi_gpio_set_drv(pin, 2); 539 } 540 541 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 542 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 543 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 544 } 545 #endif 546 break; 547 548 default: 549 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 550 break; 551 } 552 } 553 554 int board_mmc_init(bd_t *bis) 555 { 556 __maybe_unused struct mmc *mmc0, *mmc1; 557 558 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 559 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 560 if (!mmc0) 561 return -1; 562 563 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 564 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 565 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 566 if (!mmc1) 567 return -1; 568 #endif 569 570 return 0; 571 } 572 #endif 573 574 #ifdef CONFIG_SPL_BUILD 575 576 static void sunxi_spl_store_dram_size(phys_addr_t dram_size) 577 { 578 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION); 579 580 if (spl == INVALID_SPL_HEADER) 581 return; 582 583 /* Promote the header version for U-Boot proper, if needed. */ 584 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION) 585 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION; 586 587 spl->dram_size = dram_size >> 20; 588 } 589 590 void sunxi_board_init(void) 591 { 592 int power_failed = 0; 593 594 #ifdef CONFIG_SY8106A_POWER 595 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); 596 #endif 597 598 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 599 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 600 defined CONFIG_AXP818_POWER 601 power_failed = axp_init(); 602 603 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 604 defined CONFIG_AXP818_POWER 605 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); 606 #endif 607 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); 608 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); 609 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) 610 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); 611 #endif 612 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 613 defined CONFIG_AXP818_POWER 614 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); 615 #endif 616 617 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 618 defined CONFIG_AXP818_POWER 619 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); 620 #endif 621 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); 622 #if !defined(CONFIG_AXP152_POWER) 623 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); 624 #endif 625 #ifdef CONFIG_AXP209_POWER 626 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); 627 #endif 628 629 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ 630 defined(CONFIG_AXP818_POWER) 631 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); 632 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); 633 #if !defined CONFIG_AXP809_POWER 634 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); 635 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); 636 #endif 637 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); 638 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); 639 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); 640 #endif 641 642 #ifdef CONFIG_AXP818_POWER 643 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); 644 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); 645 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); 646 #endif 647 648 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 649 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); 650 #endif 651 #endif 652 printf("DRAM:"); 653 gd->ram_size = sunxi_dram_init(); 654 printf(" %d MiB\n", (int)(gd->ram_size >> 20)); 655 if (!gd->ram_size) 656 hang(); 657 658 sunxi_spl_store_dram_size(gd->ram_size); 659 660 /* 661 * Only clock up the CPU to full speed if we are reasonably 662 * assured it's being powered with suitable core voltage 663 */ 664 if (!power_failed) 665 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 666 else 667 printf("Failed to set core voltage! Can't set CPU frequency\n"); 668 } 669 #endif 670 671 #ifdef CONFIG_USB_GADGET 672 int g_dnl_board_usb_cable_connected(void) 673 { 674 struct udevice *dev; 675 struct phy phy; 676 int ret; 677 678 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev); 679 if (ret) { 680 pr_err("%s: Cannot find USB device\n", __func__); 681 return ret; 682 } 683 684 ret = generic_phy_get_by_name(dev, "usb", &phy); 685 if (ret) { 686 pr_err("failed to get %s USB PHY\n", dev->name); 687 return ret; 688 } 689 690 ret = generic_phy_init(&phy); 691 if (ret) { 692 pr_err("failed to init %s USB PHY\n", dev->name); 693 return ret; 694 } 695 696 ret = sun4i_usb_phy_vbus_detect(&phy); 697 if (ret == 1) { 698 pr_err("A charger is plugged into the OTG\n"); 699 return -ENODEV; 700 } 701 702 return ret; 703 } 704 #endif 705 706 #ifdef CONFIG_SERIAL_TAG 707 void get_board_serial(struct tag_serialnr *serialnr) 708 { 709 char *serial_string; 710 unsigned long long serial; 711 712 serial_string = env_get("serial#"); 713 714 if (serial_string) { 715 serial = simple_strtoull(serial_string, NULL, 16); 716 717 serialnr->high = (unsigned int) (serial >> 32); 718 serialnr->low = (unsigned int) (serial & 0xffffffff); 719 } else { 720 serialnr->high = 0; 721 serialnr->low = 0; 722 } 723 } 724 #endif 725 726 /* 727 * Check the SPL header for the "sunxi" variant. If found: parse values 728 * that might have been passed by the loader ("fel" utility), and update 729 * the environment accordingly. 730 */ 731 static void parse_spl_header(const uint32_t spl_addr) 732 { 733 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION); 734 735 if (spl == INVALID_SPL_HEADER) 736 return; 737 738 if (!spl->fel_script_address) 739 return; 740 741 if (spl->fel_uEnv_length != 0) { 742 /* 743 * data is expected in uEnv.txt compatible format, so "env 744 * import -t" the string(s) at fel_script_address right away. 745 */ 746 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address, 747 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL); 748 return; 749 } 750 /* otherwise assume .scr format (mkimage-type script) */ 751 env_set_hex("fel_scriptaddr", spl->fel_script_address); 752 } 753 754 /* 755 * Note this function gets called multiple times. 756 * It must not make any changes to env variables which already exist. 757 */ 758 static void setup_environment(const void *fdt) 759 { 760 char serial_string[17] = { 0 }; 761 unsigned int sid[4]; 762 uint8_t mac_addr[6]; 763 char ethaddr[16]; 764 int i, ret; 765 766 ret = sunxi_get_sid(sid); 767 if (ret == 0 && sid[0] != 0) { 768 /* 769 * The single words 1 - 3 of the SID have quite a few bits 770 * which are the same on many models, so we take a crc32 771 * of all 3 words, to get a more unique value. 772 * 773 * Note we only do this on newer SoCs as we cannot change 774 * the algorithm on older SoCs since those have been using 775 * fixed mac-addresses based on only using word 3 for a 776 * long time and changing a fixed mac-address with an 777 * u-boot update is not good. 778 */ 779 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ 780 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ 781 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) 782 sid[3] = crc32(0, (unsigned char *)&sid[1], 12); 783 #endif 784 785 /* Ensure the NIC specific bytes of the mac are not all 0 */ 786 if ((sid[3] & 0xffffff) == 0) 787 sid[3] |= 0x800000; 788 789 for (i = 0; i < 4; i++) { 790 sprintf(ethaddr, "ethernet%d", i); 791 if (!fdt_get_alias(fdt, ethaddr)) 792 continue; 793 794 if (i == 0) 795 strcpy(ethaddr, "ethaddr"); 796 else 797 sprintf(ethaddr, "eth%daddr", i); 798 799 if (env_get(ethaddr)) 800 continue; 801 802 /* Non OUI / registered MAC address */ 803 mac_addr[0] = (i << 4) | 0x02; 804 mac_addr[1] = (sid[0] >> 0) & 0xff; 805 mac_addr[2] = (sid[3] >> 24) & 0xff; 806 mac_addr[3] = (sid[3] >> 16) & 0xff; 807 mac_addr[4] = (sid[3] >> 8) & 0xff; 808 mac_addr[5] = (sid[3] >> 0) & 0xff; 809 810 eth_env_set_enetaddr(ethaddr, mac_addr); 811 } 812 813 if (!env_get("serial#")) { 814 snprintf(serial_string, sizeof(serial_string), 815 "%08x%08x", sid[0], sid[3]); 816 817 env_set("serial#", serial_string); 818 } 819 } 820 } 821 822 int misc_init_r(void) 823 { 824 uint boot; 825 826 env_set("fel_booted", NULL); 827 env_set("fel_scriptaddr", NULL); 828 env_set("mmc_bootdev", NULL); 829 830 boot = sunxi_get_boot_device(); 831 /* determine if we are running in FEL mode */ 832 if (boot == BOOT_DEVICE_BOARD) { 833 env_set("fel_booted", "1"); 834 parse_spl_header(SPL_ADDR); 835 /* or if we booted from MMC, and which one */ 836 } else if (boot == BOOT_DEVICE_MMC1) { 837 env_set("mmc_bootdev", "0"); 838 } else if (boot == BOOT_DEVICE_MMC2) { 839 env_set("mmc_bootdev", "1"); 840 } 841 842 setup_environment(gd->fdt_blob); 843 844 #ifdef CONFIG_USB_ETHER 845 usb_ether_init(); 846 #endif 847 848 return 0; 849 } 850 851 int ft_board_setup(void *blob, bd_t *bd) 852 { 853 int __maybe_unused r; 854 855 /* 856 * Call setup_environment again in case the boot fdt has 857 * ethernet aliases the u-boot copy does not have. 858 */ 859 setup_environment(blob); 860 861 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 862 r = sunxi_simplefb_setup(blob); 863 if (r) 864 return r; 865 #endif 866 return 0; 867 } 868 869 #ifdef CONFIG_SPL_LOAD_FIT 870 int board_fit_config_name_match(const char *name) 871 { 872 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION); 873 const char *cmp_str = (const char *)spl; 874 875 /* Check if there is a DT name stored in the SPL header and use that. */ 876 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) { 877 cmp_str += spl->dt_name_offset; 878 } else { 879 #ifdef CONFIG_DEFAULT_DEVICE_TREE 880 cmp_str = CONFIG_DEFAULT_DEVICE_TREE; 881 #else 882 return 0; 883 #endif 884 }; 885 886 #ifdef CONFIG_PINE64_DT_SELECTION 887 /* Differentiate the two Pine64 board DTs by their DRAM size. */ 888 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) { 889 if ((gd->ram_size > 512 * 1024 * 1024)) 890 return !strstr(name, "plus"); 891 else 892 return !!strstr(name, "plus"); 893 } else { 894 return strcmp(name, cmp_str); 895 } 896 #endif 897 return strcmp(name, cmp_str); 898 } 899 #endif 900