1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #ifdef CONFIG_AXP152_POWER 17 #include <axp152.h> 18 #endif 19 #ifdef CONFIG_AXP209_POWER 20 #include <axp209.h> 21 #endif 22 #ifdef CONFIG_AXP221_POWER 23 #include <axp221.h> 24 #endif 25 #include <asm/arch/clock.h> 26 #include <asm/arch/cpu.h> 27 #include <asm/arch/display.h> 28 #include <asm/arch/dram.h> 29 #include <asm/arch/gpio.h> 30 #include <asm/arch/mmc.h> 31 #include <asm/arch/usbc.h> 32 #include <asm/io.h> 33 #include <linux/usb/musb.h> 34 #include <net.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 /* add board specific code here */ 39 int board_init(void) 40 { 41 int id_pfr1; 42 43 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 44 45 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 46 debug("id_pfr1: 0x%08x\n", id_pfr1); 47 /* Generic Timer Extension available? */ 48 if ((id_pfr1 >> 16) & 0xf) { 49 debug("Setting CNTFRQ\n"); 50 /* CNTFRQ == 24 MHz */ 51 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); 52 } 53 54 return 0; 55 } 56 57 int dram_init(void) 58 { 59 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 60 61 return 0; 62 } 63 64 #ifdef CONFIG_GENERIC_MMC 65 static void mmc_pinmux_setup(int sdc) 66 { 67 unsigned int pin; 68 69 switch (sdc) { 70 case 0: 71 /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */ 72 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 73 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0); 74 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 75 sunxi_gpio_set_drv(pin, 2); 76 } 77 break; 78 79 case 1: 80 /* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */ 81 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 82 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG3_SDC1); 83 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 84 sunxi_gpio_set_drv(pin, 2); 85 } 86 break; 87 88 case 2: 89 /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */ 90 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 91 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2); 92 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 93 sunxi_gpio_set_drv(pin, 2); 94 } 95 break; 96 97 case 3: 98 /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */ 99 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 100 sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3); 101 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 102 sunxi_gpio_set_drv(pin, 2); 103 } 104 break; 105 106 default: 107 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 108 break; 109 } 110 } 111 112 int board_mmc_init(bd_t *bis) 113 { 114 __maybe_unused struct mmc *mmc0, *mmc1; 115 __maybe_unused char buf[512]; 116 117 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 118 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 119 if (!mmc0) 120 return -1; 121 122 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 123 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 124 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 125 if (!mmc1) 126 return -1; 127 #endif 128 129 #if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 130 /* 131 * Both mmc0 and mmc2 are bootable, figure out where we're booting 132 * from. Try mmc0 first, just like the brom does. 133 */ 134 if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 && 135 mmc0->block_dev.block_read(0, 16, 1, buf) == 1) { 136 buf[12] = 0; 137 if (strcmp(&buf[4], "eGON.BT0") == 0) 138 return 0; 139 } 140 141 /* no bootable card in mmc0, so we must be booting from mmc2, swap */ 142 mmc0->block_dev.dev = 1; 143 mmc1->block_dev.dev = 0; 144 #endif 145 146 return 0; 147 } 148 #endif 149 150 void i2c_init_board(void) 151 { 152 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0); 153 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0); 154 clock_twi_onoff(0, 1); 155 } 156 157 #ifdef CONFIG_SPL_BUILD 158 void sunxi_board_init(void) 159 { 160 int power_failed = 0; 161 unsigned long ramsize; 162 163 #ifdef CONFIG_AXP152_POWER 164 power_failed = axp152_init(); 165 power_failed |= axp152_set_dcdc2(1400); 166 power_failed |= axp152_set_dcdc3(1500); 167 power_failed |= axp152_set_dcdc4(1250); 168 power_failed |= axp152_set_ldo2(3000); 169 #endif 170 #ifdef CONFIG_AXP209_POWER 171 power_failed |= axp209_init(); 172 power_failed |= axp209_set_dcdc2(1400); 173 power_failed |= axp209_set_dcdc3(1250); 174 power_failed |= axp209_set_ldo2(3000); 175 power_failed |= axp209_set_ldo3(2800); 176 power_failed |= axp209_set_ldo4(2800); 177 #endif 178 #ifdef CONFIG_AXP221_POWER 179 power_failed = axp221_init(); 180 power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT); 181 power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */ 182 power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */ 183 #ifdef CONFIG_MACH_SUN6I 184 power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */ 185 #else 186 power_failed |= axp221_set_dcdc4(0); /* A23:unused */ 187 #endif 188 power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */ 189 power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); 190 power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); 191 power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); 192 power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); 193 power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); 194 power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT); 195 #endif 196 197 printf("DRAM:"); 198 ramsize = sunxi_dram_init(); 199 printf(" %lu MiB\n", ramsize >> 20); 200 if (!ramsize) 201 hang(); 202 203 /* 204 * Only clock up the CPU to full speed if we are reasonably 205 * assured it's being powered with suitable core voltage 206 */ 207 if (!power_failed) 208 clock_set_pll1(CONFIG_CLK_FULL_SPEED); 209 else 210 printf("Failed to set core voltage! Can't set CPU frequency\n"); 211 } 212 #endif 213 214 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) 215 static struct musb_hdrc_config musb_config = { 216 .multipoint = 1, 217 .dyn_fifo = 1, 218 .num_eps = 6, 219 .ram_bits = 11, 220 }; 221 222 static struct musb_hdrc_platform_data musb_plat = { 223 #if defined(CONFIG_MUSB_HOST) 224 .mode = MUSB_HOST, 225 #else 226 .mode = MUSB_PERIPHERAL, 227 #endif 228 .config = &musb_config, 229 .power = 250, 230 .platform_ops = &sunxi_musb_ops, 231 }; 232 #endif 233 234 #ifdef CONFIG_MISC_INIT_R 235 int misc_init_r(void) 236 { 237 unsigned int sid[4]; 238 239 if (!getenv("ethaddr") && sunxi_get_sid(sid) == 0 && 240 sid[0] != 0 && sid[3] != 0) { 241 uint8_t mac_addr[6]; 242 243 mac_addr[0] = 0x02; /* Non OUI / registered MAC address */ 244 mac_addr[1] = (sid[0] >> 0) & 0xff; 245 mac_addr[2] = (sid[3] >> 24) & 0xff; 246 mac_addr[3] = (sid[3] >> 16) & 0xff; 247 mac_addr[4] = (sid[3] >> 8) & 0xff; 248 mac_addr[5] = (sid[3] >> 0) & 0xff; 249 250 eth_setenv_enetaddr("ethaddr", mac_addr); 251 } 252 253 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) 254 musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE); 255 #endif 256 return 0; 257 } 258 #endif 259 260 #ifdef CONFIG_OF_BOARD_SETUP 261 int ft_board_setup(void *blob, bd_t *bd) 262 { 263 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 264 return sunxi_simplefb_setup(blob); 265 #endif 266 } 267 #endif /* CONFIG_OF_BOARD_SETUP */ 268