1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #ifdef CONFIG_AXP152_POWER 17 #include <axp152.h> 18 #endif 19 #ifdef CONFIG_AXP209_POWER 20 #include <axp209.h> 21 #endif 22 #ifdef CONFIG_AXP221_POWER 23 #include <axp221.h> 24 #endif 25 #include <asm/arch/clock.h> 26 #include <asm/arch/cpu.h> 27 #include <asm/arch/display.h> 28 #include <asm/arch/dram.h> 29 #include <asm/arch/gpio.h> 30 #include <asm/arch/mmc.h> 31 #include <asm/arch/usb_phy.h> 32 #include <asm/gpio.h> 33 #include <asm/io.h> 34 #include <net.h> 35 36 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 37 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 38 int soft_i2c_gpio_sda; 39 int soft_i2c_gpio_scl; 40 41 static int soft_i2c_board_init(void) 42 { 43 int ret; 44 45 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 46 if (soft_i2c_gpio_sda < 0) { 47 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 48 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 49 return soft_i2c_gpio_sda; 50 } 51 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 52 if (ret) { 53 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 54 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 55 return ret; 56 } 57 58 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 59 if (soft_i2c_gpio_scl < 0) { 60 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 61 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 62 return soft_i2c_gpio_scl; 63 } 64 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 65 if (ret) { 66 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 67 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 68 return ret; 69 } 70 71 return 0; 72 } 73 #else 74 static int soft_i2c_board_init(void) { return 0; } 75 #endif 76 77 DECLARE_GLOBAL_DATA_PTR; 78 79 /* add board specific code here */ 80 int board_init(void) 81 { 82 int id_pfr1, ret; 83 84 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 85 86 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 87 debug("id_pfr1: 0x%08x\n", id_pfr1); 88 /* Generic Timer Extension available? */ 89 if ((id_pfr1 >> 16) & 0xf) { 90 debug("Setting CNTFRQ\n"); 91 /* CNTFRQ == 24 MHz */ 92 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); 93 } 94 95 ret = axp_gpio_init(); 96 if (ret) 97 return ret; 98 99 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 100 return soft_i2c_board_init(); 101 } 102 103 int dram_init(void) 104 { 105 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 106 107 return 0; 108 } 109 110 #ifdef CONFIG_GENERIC_MMC 111 static void mmc_pinmux_setup(int sdc) 112 { 113 unsigned int pin; 114 __maybe_unused int pins; 115 116 switch (sdc) { 117 case 0: 118 /* SDC0: PF0-PF5 */ 119 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 120 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 121 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 122 sunxi_gpio_set_drv(pin, 2); 123 } 124 break; 125 126 case 1: 127 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 128 129 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 130 if (pins == SUNXI_GPIO_H) { 131 /* SDC1: PH22-PH-27 */ 132 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 133 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 134 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 135 sunxi_gpio_set_drv(pin, 2); 136 } 137 } else { 138 /* SDC1: PG0-PG5 */ 139 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 140 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 141 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 142 sunxi_gpio_set_drv(pin, 2); 143 } 144 } 145 #elif defined(CONFIG_MACH_SUN5I) 146 /* SDC1: PG3-PG8 */ 147 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 148 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 149 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 150 sunxi_gpio_set_drv(pin, 2); 151 } 152 #elif defined(CONFIG_MACH_SUN6I) 153 /* SDC1: PG0-PG5 */ 154 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 155 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 156 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 157 sunxi_gpio_set_drv(pin, 2); 158 } 159 #elif defined(CONFIG_MACH_SUN8I) 160 if (pins == SUNXI_GPIO_D) { 161 /* SDC1: PD2-PD7 */ 162 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 163 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 164 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 165 sunxi_gpio_set_drv(pin, 2); 166 } 167 } else { 168 /* SDC1: PG0-PG5 */ 169 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 170 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 171 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 172 sunxi_gpio_set_drv(pin, 2); 173 } 174 } 175 #endif 176 break; 177 178 case 2: 179 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 180 181 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 182 /* SDC2: PC6-PC11 */ 183 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 184 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 185 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 186 sunxi_gpio_set_drv(pin, 2); 187 } 188 #elif defined(CONFIG_MACH_SUN5I) 189 if (pins == SUNXI_GPIO_E) { 190 /* SDC2: PE4-PE9 */ 191 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 192 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 193 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 194 sunxi_gpio_set_drv(pin, 2); 195 } 196 } else { 197 /* SDC2: PC6-PC15 */ 198 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 199 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 200 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 201 sunxi_gpio_set_drv(pin, 2); 202 } 203 } 204 #elif defined(CONFIG_MACH_SUN6I) 205 if (pins == SUNXI_GPIO_A) { 206 /* SDC2: PA9-PA14 */ 207 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 208 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 209 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 210 sunxi_gpio_set_drv(pin, 2); 211 } 212 } else { 213 /* SDC2: PC6-PC15, PC24 */ 214 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 215 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 216 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 217 sunxi_gpio_set_drv(pin, 2); 218 } 219 220 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 221 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 222 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 223 } 224 #elif defined(CONFIG_MACH_SUN8I) 225 /* SDC2: PC5-PC6, PC8-PC16 */ 226 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 227 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 228 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 229 sunxi_gpio_set_drv(pin, 2); 230 } 231 232 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 233 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 234 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 235 sunxi_gpio_set_drv(pin, 2); 236 } 237 #endif 238 break; 239 240 case 3: 241 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 242 243 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 244 /* SDC3: PI4-PI9 */ 245 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 246 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 247 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 248 sunxi_gpio_set_drv(pin, 2); 249 } 250 #elif defined(CONFIG_MACH_SUN6I) 251 if (pins == SUNXI_GPIO_A) { 252 /* SDC3: PA9-PA14 */ 253 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 254 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 255 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 256 sunxi_gpio_set_drv(pin, 2); 257 } 258 } else { 259 /* SDC3: PC6-PC15, PC24 */ 260 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 261 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 262 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 263 sunxi_gpio_set_drv(pin, 2); 264 } 265 266 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 267 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 268 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 269 } 270 #endif 271 break; 272 273 default: 274 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 275 break; 276 } 277 } 278 279 int board_mmc_init(bd_t *bis) 280 { 281 __maybe_unused struct mmc *mmc0, *mmc1; 282 __maybe_unused char buf[512]; 283 284 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 285 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 286 if (!mmc0) 287 return -1; 288 289 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 290 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 291 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 292 if (!mmc1) 293 return -1; 294 #endif 295 296 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 297 /* 298 * On systems with an emmc (mmc2), figure out if we are booting from 299 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. 300 * are searched there first. Note we only do this for u-boot proper, 301 * not for the SPL, see spl_boot_device(). 302 */ 303 if (!sunxi_mmc_has_egon_boot_signature(mmc0) && 304 sunxi_mmc_has_egon_boot_signature(mmc1)) { 305 /* Booting from emmc / mmc2, swap */ 306 mmc0->block_dev.dev = 1; 307 mmc1->block_dev.dev = 0; 308 } 309 #endif 310 311 return 0; 312 } 313 #endif 314 315 void i2c_init_board(void) 316 { 317 #ifdef CONFIG_I2C0_ENABLE 318 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) 319 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 320 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 321 clock_twi_onoff(0, 1); 322 #elif defined(CONFIG_MACH_SUN6I) 323 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 324 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 325 clock_twi_onoff(0, 1); 326 #elif defined(CONFIG_MACH_SUN8I) 327 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 328 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 329 clock_twi_onoff(0, 1); 330 #endif 331 #endif 332 333 #ifdef CONFIG_I2C1_ENABLE 334 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 335 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 336 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 337 clock_twi_onoff(1, 1); 338 #elif defined(CONFIG_MACH_SUN5I) 339 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 340 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 341 clock_twi_onoff(1, 1); 342 #elif defined(CONFIG_MACH_SUN6I) 343 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 344 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 345 clock_twi_onoff(1, 1); 346 #elif defined(CONFIG_MACH_SUN8I) 347 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 348 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 349 clock_twi_onoff(1, 1); 350 #endif 351 #endif 352 353 #ifdef CONFIG_I2C2_ENABLE 354 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 355 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 356 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 357 clock_twi_onoff(2, 1); 358 #elif defined(CONFIG_MACH_SUN5I) 359 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 360 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 361 clock_twi_onoff(2, 1); 362 #elif defined(CONFIG_MACH_SUN6I) 363 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 364 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 365 clock_twi_onoff(2, 1); 366 #elif defined(CONFIG_MACH_SUN8I) 367 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 368 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 369 clock_twi_onoff(2, 1); 370 #endif 371 #endif 372 373 #ifdef CONFIG_I2C3_ENABLE 374 #if defined(CONFIG_MACH_SUN6I) 375 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 376 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 377 clock_twi_onoff(3, 1); 378 #elif defined(CONFIG_MACH_SUN7I) 379 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 380 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 381 clock_twi_onoff(3, 1); 382 #endif 383 #endif 384 385 #ifdef CONFIG_I2C4_ENABLE 386 #if defined(CONFIG_MACH_SUN7I) 387 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 388 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 389 clock_twi_onoff(4, 1); 390 #endif 391 #endif 392 } 393 394 #ifdef CONFIG_SPL_BUILD 395 void sunxi_board_init(void) 396 { 397 int power_failed = 0; 398 unsigned long ramsize; 399 400 #ifdef CONFIG_AXP152_POWER 401 power_failed = axp152_init(); 402 power_failed |= axp152_set_dcdc2(1400); 403 power_failed |= axp152_set_dcdc3(1500); 404 power_failed |= axp152_set_dcdc4(1250); 405 power_failed |= axp152_set_ldo2(3000); 406 #endif 407 #ifdef CONFIG_AXP209_POWER 408 power_failed |= axp209_init(); 409 power_failed |= axp209_set_dcdc2(1400); 410 power_failed |= axp209_set_dcdc3(1250); 411 power_failed |= axp209_set_ldo2(3000); 412 power_failed |= axp209_set_ldo3(2800); 413 power_failed |= axp209_set_ldo4(2800); 414 #endif 415 #ifdef CONFIG_AXP221_POWER 416 power_failed = axp221_init(); 417 power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT); 418 power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */ 419 power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */ 420 #ifdef CONFIG_MACH_SUN6I 421 power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */ 422 #else 423 power_failed |= axp221_set_dcdc4(0); /* A23:unused */ 424 #endif 425 power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */ 426 power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); 427 power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); 428 power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); 429 power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); 430 power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); 431 power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT); 432 #endif 433 434 printf("DRAM:"); 435 ramsize = sunxi_dram_init(); 436 printf(" %lu MiB\n", ramsize >> 20); 437 if (!ramsize) 438 hang(); 439 440 /* 441 * Only clock up the CPU to full speed if we are reasonably 442 * assured it's being powered with suitable core voltage 443 */ 444 if (!power_failed) 445 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 446 else 447 printf("Failed to set core voltage! Can't set CPU frequency\n"); 448 } 449 #endif 450 451 #ifdef CONFIG_USB_GADGET 452 int g_dnl_board_usb_cable_connected(void) 453 { 454 return sunxi_usb_phy_vbus_detect(0); 455 } 456 #endif 457 458 #ifdef CONFIG_SERIAL_TAG 459 void get_board_serial(struct tag_serialnr *serialnr) 460 { 461 char *serial_string; 462 unsigned long long serial; 463 464 serial_string = getenv("serial#"); 465 466 if (serial_string) { 467 serial = simple_strtoull(serial_string, NULL, 16); 468 469 serialnr->high = (unsigned int) (serial >> 32); 470 serialnr->low = (unsigned int) (serial & 0xffffffff); 471 } else { 472 serialnr->high = 0; 473 serialnr->low = 0; 474 } 475 } 476 #endif 477 478 #ifdef CONFIG_MISC_INIT_R 479 int misc_init_r(void) 480 { 481 char serial_string[17] = { 0 }; 482 unsigned int sid[4]; 483 uint8_t mac_addr[6]; 484 int ret; 485 486 ret = sunxi_get_sid(sid); 487 if (ret == 0 && sid[0] != 0 && sid[3] != 0) { 488 if (!getenv("ethaddr")) { 489 /* Non OUI / registered MAC address */ 490 mac_addr[0] = 0x02; 491 mac_addr[1] = (sid[0] >> 0) & 0xff; 492 mac_addr[2] = (sid[3] >> 24) & 0xff; 493 mac_addr[3] = (sid[3] >> 16) & 0xff; 494 mac_addr[4] = (sid[3] >> 8) & 0xff; 495 mac_addr[5] = (sid[3] >> 0) & 0xff; 496 497 eth_setenv_enetaddr("ethaddr", mac_addr); 498 } 499 500 if (!getenv("serial#")) { 501 snprintf(serial_string, sizeof(serial_string), 502 "%08x%08x", sid[0], sid[3]); 503 504 setenv("serial#", serial_string); 505 } 506 } 507 508 #ifndef CONFIG_MACH_SUN9I 509 ret = sunxi_usb_phy_probe(); 510 if (ret) 511 return ret; 512 #endif 513 sunxi_musb_board_init(); 514 515 return 0; 516 } 517 #endif 518 519 #ifdef CONFIG_OF_BOARD_SETUP 520 int ft_board_setup(void *blob, bd_t *bd) 521 { 522 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 523 return sunxi_simplefb_setup(blob); 524 #endif 525 } 526 #endif /* CONFIG_OF_BOARD_SETUP */ 527