1 #include <common.h> 2 #include <ahci.h> 3 #include <dm.h> 4 #include <scsi.h> 5 #include <errno.h> 6 #include <asm/io.h> 7 #include <asm/gpio.h> 8 9 #define AHCI_PHYCS0R 0x00c0 10 #define AHCI_PHYCS1R 0x00c4 11 #define AHCI_PHYCS2R 0x00c8 12 #define AHCI_RWCR 0x00fc 13 14 /* This magic PHY initialisation was taken from the Allwinner releases 15 * and Linux driver, but is completely undocumented. 16 */ 17 static int sunxi_ahci_phy_init(u8 *reg_base) 18 { 19 u32 reg_val; 20 int timeout; 21 22 writel(0, reg_base + AHCI_RWCR); 23 mdelay(5); 24 25 setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); 26 clrsetbits_le32(reg_base + AHCI_PHYCS0R, 27 (0x7 << 24), 28 (0x5 << 24) | (0x1 << 23) | (0x1 << 18)); 29 clrsetbits_le32(reg_base + AHCI_PHYCS1R, 30 (0x3 << 16) | (0x1f << 8) | (0x3 << 6), 31 (0x2 << 16) | (0x6 << 8) | (0x2 << 6)); 32 setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15)); 33 clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); 34 clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); 35 clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); 36 mdelay(5); 37 38 setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); 39 40 timeout = 250; /* Power up takes approx 50 us */ 41 for (;;) { 42 reg_val = readl(reg_base + AHCI_PHYCS0R) & (0x7 << 28); 43 if (reg_val == (0x2 << 28)) 44 break; 45 if (--timeout == 0) { 46 printf("AHCI PHY power up failed.\n"); 47 return -EIO; 48 } 49 udelay(1); 50 }; 51 52 setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24)); 53 54 timeout = 100; /* Calibration takes approx 10 us */ 55 for (;;) { 56 reg_val = readl(reg_base + AHCI_PHYCS2R) & (0x1 << 24); 57 if (reg_val == 0x0) 58 break; 59 if (--timeout == 0) { 60 printf("AHCI PHY calibration failed.\n"); 61 return -EIO; 62 } 63 udelay(1); 64 } 65 66 mdelay(15); 67 68 writel(0x7, reg_base + AHCI_RWCR); 69 70 return 0; 71 } 72 73 #ifndef CONFIG_DM_SCSI 74 void scsi_init(void) 75 { 76 if (sunxi_ahci_phy_init((u8 *)SUNXI_SATA_BASE) < 0) 77 return; 78 79 ahci_init((void __iomem *)SUNXI_SATA_BASE); 80 } 81 #else 82 static int sunxi_sata_probe(struct udevice *dev) 83 { 84 ulong base; 85 u8 *reg; 86 int ret; 87 88 base = dev_read_addr(dev); 89 if (base == FDT_ADDR_T_NONE) { 90 debug("%s: Failed to find address (err=%d\n)", __func__, ret); 91 return -EINVAL; 92 } 93 reg = (u8 *)base; 94 ret = sunxi_ahci_phy_init(reg); 95 if (ret) { 96 debug("%s: Failed to init phy (err=%d\n)", __func__, ret); 97 return ret; 98 } 99 ret = ahci_probe_scsi(dev, base); 100 if (ret) { 101 debug("%s: Failed to probe (err=%d\n)", __func__, ret); 102 return ret; 103 } 104 105 return 0; 106 } 107 108 static int sunxi_sata_bind(struct udevice *dev) 109 { 110 struct udevice *scsi_dev; 111 int ret; 112 113 ret = ahci_bind_scsi(dev, &scsi_dev); 114 if (ret) { 115 debug("%s: Failed to bind (err=%d\n)", __func__, ret); 116 return ret; 117 } 118 119 return 0; 120 } 121 122 static const struct udevice_id sunxi_ahci_ids[] = { 123 { .compatible = "allwinner,sun4i-a10-ahci" }, 124 { } 125 }; 126 127 U_BOOT_DRIVER(ahci_sunxi_drv) = { 128 .name = "ahci_sunxi", 129 .id = UCLASS_AHCI, 130 .of_match = sunxi_ahci_ids, 131 .bind = sunxi_sata_bind, 132 .probe = sunxi_sata_probe, 133 }; 134 #endif 135