1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2014, STMicroelectronics - All Rights Reserved 4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <miiphy.h> 10 #include <asm/arch/stv0991_periph.h> 11 #include <asm/arch/stv0991_defs.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/gpio.h> 14 #include <netdev.h> 15 #include <asm/io.h> 16 #include <dm/platform_data/serial_pl01x.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 struct gpio_regs *const gpioa_regs = 21 (struct gpio_regs *) GPIOA_BASE_ADDR; 22 23 #ifndef CONFIG_OF_CONTROL 24 static const struct pl01x_serial_platdata serial_platdata = { 25 .base = 0x80406000, 26 .type = TYPE_PL011, 27 .clock = 2700 * 1000, 28 }; 29 30 U_BOOT_DEVICE(stv09911_serials) = { 31 .name = "serial_pl01x", 32 .platdata = &serial_platdata, 33 }; 34 #endif 35 36 #ifdef CONFIG_SHOW_BOOT_PROGRESS 37 void show_boot_progress(int progress) 38 { 39 printf("%i\n", progress); 40 } 41 #endif 42 43 void enable_eth_phy(void) 44 { 45 /* Set GPIOA_06 pad HIGH (Appli board)*/ 46 writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir); 47 writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data); 48 } 49 int board_eth_enable(void) 50 { 51 stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4); 52 clock_setup(ETH_CLOCK_CFG); 53 enable_eth_phy(); 54 return 0; 55 } 56 57 int board_qspi_enable(void) 58 { 59 stv0991_pinmux_config(QSPI_CS_CLK_PAD); 60 clock_setup(QSPI_CLOCK_CFG); 61 return 0; 62 } 63 64 /* 65 * Miscellaneous platform dependent initialisations 66 */ 67 int board_init(void) 68 { 69 board_eth_enable(); 70 board_qspi_enable(); 71 return 0; 72 } 73 74 int board_uart_init(void) 75 { 76 stv0991_pinmux_config(UART_GPIOC_30_31); 77 clock_setup(UART_CLOCK_CFG); 78 return 0; 79 } 80 81 #ifdef CONFIG_BOARD_EARLY_INIT_F 82 int board_early_init_f(void) 83 { 84 board_uart_init(); 85 return 0; 86 } 87 #endif 88 89 int dram_init(void) 90 { 91 gd->ram_size = PHYS_SDRAM_1_SIZE; 92 return 0; 93 } 94 95 int dram_init_banksize(void) 96 { 97 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 98 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 99 100 return 0; 101 } 102 103 #ifdef CONFIG_CMD_NET 104 int board_eth_init(bd_t *bis) 105 { 106 int ret = 0; 107 108 #if defined(CONFIG_ETH_DESIGNWARE) 109 u32 interface = PHY_INTERFACE_MODE_MII; 110 if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0) 111 ret++; 112 #endif 113 return ret; 114 } 115 #endif 116