1 /* 2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <asm/io.h> 10 #include <asm/arch/ddr.h> 11 #include <power/pmic.h> 12 #include <power/stpmu1.h> 13 14 #ifdef CONFIG_PMIC_STPMU1 15 int board_ddr_power_init(void) 16 { 17 struct udevice *dev; 18 int ret; 19 20 ret = uclass_get_device_by_driver(UCLASS_PMIC, 21 DM_GET_DRIVER(pmic_stpmu1), &dev); 22 if (ret) 23 /* No PMIC on board */ 24 return 0; 25 26 /* Set LDO3 to sync mode */ 27 ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3)); 28 if (ret < 0) 29 return ret; 30 31 ret &= ~STPMU1_LDO3_MODE; 32 ret &= ~STPMU1_LDO12356_OUTPUT_MASK; 33 ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT; 34 35 ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3), 36 ret); 37 if (ret < 0) 38 return ret; 39 40 /* Set BUCK2 to 1.35V */ 41 ret = pmic_clrsetbits(dev, 42 STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2), 43 STPMU1_BUCK_OUTPUT_MASK, 44 STPMU1_BUCK2_1350000V); 45 if (ret < 0) 46 return ret; 47 48 /* Enable BUCK2 and VREF */ 49 ret = pmic_clrsetbits(dev, 50 STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2), 51 STPMU1_BUCK_EN, STPMU1_BUCK_EN); 52 if (ret < 0) 53 return ret; 54 55 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); 56 57 ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG, 58 STPMU1_VREF_EN, STPMU1_VREF_EN); 59 if (ret < 0) 60 return ret; 61 62 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); 63 64 /* Enable LDO3 */ 65 ret = pmic_clrsetbits(dev, 66 STPMU1_LDOX_CTRL_REG(STPMU1_LDO3), 67 STPMU1_LDO_EN, STPMU1_LDO_EN); 68 if (ret < 0) 69 return ret; 70 71 mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS); 72 73 return 0; 74 } 75 #endif 76