1 /* 2 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <lcd.h> 11 #include <ram.h> 12 #include <spl.h> 13 #include <splash.h> 14 #include <st_logo_data.h> 15 #include <video.h> 16 #include <asm/io.h> 17 #include <asm/armv7m.h> 18 #include <asm/arch/stm32.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/syscfg.h> 21 #include <asm/gpio.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size) 26 { 27 int mr_node; 28 29 mr_node = fdt_path_offset(gd->fdt_blob, "/memory"); 30 if (mr_node < 0) 31 return mr_node; 32 *mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node, 33 "reg", 0, mr_size, false); 34 debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size); 35 36 return 0; 37 } 38 int dram_init(void) 39 { 40 int rv; 41 fdt_addr_t mr_base, mr_size; 42 43 #ifndef CONFIG_SUPPORT_SPL 44 struct udevice *dev; 45 rv = uclass_get_device(UCLASS_RAM, 0, &dev); 46 if (rv) { 47 debug("DRAM init failed: %d\n", rv); 48 return rv; 49 } 50 51 #endif 52 rv = get_memory_base_size(&mr_base, &mr_size); 53 if (rv) 54 return rv; 55 gd->ram_size = mr_size; 56 gd->ram_top = mr_base; 57 58 return rv; 59 } 60 61 int dram_init_banksize(void) 62 { 63 fdt_addr_t mr_base, mr_size; 64 get_memory_base_size(&mr_base, &mr_size); 65 /* 66 * Fill in global info with description of SRAM configuration 67 */ 68 gd->bd->bi_dram[0].start = mr_base; 69 gd->bd->bi_dram[0].size = mr_size; 70 71 return 0; 72 } 73 74 int board_early_init_f(void) 75 { 76 return 0; 77 } 78 79 #ifdef CONFIG_SPL_BUILD 80 #ifdef CONFIG_SPL_OS_BOOT 81 int spl_start_uboot(void) 82 { 83 debug("SPL: booting kernel\n"); 84 /* break into full u-boot on 'c' */ 85 return serial_tstc() && serial_getc() == 'c'; 86 } 87 #endif 88 89 int spl_dram_init(void) 90 { 91 struct udevice *dev; 92 int rv; 93 rv = uclass_get_device(UCLASS_RAM, 0, &dev); 94 if (rv) 95 debug("DRAM init failed: %d\n", rv); 96 return rv; 97 } 98 void spl_board_init(void) 99 { 100 spl_dram_init(); 101 preloader_console_init(); 102 arch_cpu_init(); /* to configure mpu for sdram rw permissions */ 103 } 104 u32 spl_boot_device(void) 105 { 106 return BOOT_DEVICE_XIP; 107 } 108 109 #endif 110 u32 get_board_rev(void) 111 { 112 return 0; 113 } 114 115 int board_late_init(void) 116 { 117 struct gpio_desc gpio = {}; 118 int node; 119 120 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1"); 121 if (node < 0) 122 return -1; 123 124 gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio, 125 GPIOD_IS_OUT); 126 127 if (dm_gpio_is_valid(&gpio)) { 128 dm_gpio_set_value(&gpio, 0); 129 mdelay(10); 130 dm_gpio_set_value(&gpio, 1); 131 } 132 133 /* read button 1*/ 134 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1"); 135 if (node < 0) 136 return -1; 137 138 gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0, 139 &gpio, GPIOD_IS_IN); 140 141 if (dm_gpio_is_valid(&gpio)) { 142 if (dm_gpio_get_value(&gpio)) 143 puts("usr button is at HIGH LEVEL\n"); 144 else 145 puts("usr button is at LOW LEVEL\n"); 146 } 147 148 return 0; 149 } 150 151 int board_init(void) 152 { 153 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; 154 155 #ifdef CONFIG_ETH_DESIGNWARE 156 /* Set >RMII mode */ 157 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; 158 #endif 159 160 #if defined(CONFIG_CMD_BMP) 161 bmp_display((ulong)stmicroelectronics_uboot_logo_8bit_rle, 162 BMP_ALIGN_CENTER, BMP_ALIGN_CENTER); 163 #endif /* CONFIG_CMD_BMP */ 164 165 return 0; 166 } 167