1 /* 2 * (C) Copyright 2016 3 * Vikas Manocha, <vikas.manocha@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/armv7m.h> 11 #include <asm/arch/stm32.h> 12 #include <asm/arch/gpio.h> 13 #include <asm/arch/rcc.h> 14 #include <asm/arch/fmc.h> 15 #include <dm/platdata.h> 16 #include <dm/platform_data/serial_stm32x7.h> 17 #include <asm/arch/stm32_periph.h> 18 #include <asm/arch/stm32_defs.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 const struct stm32_gpio_ctl gpio_ctl_gpout = { 23 .mode = STM32_GPIO_MODE_OUT, 24 .otype = STM32_GPIO_OTYPE_PP, 25 .speed = STM32_GPIO_SPEED_50M, 26 .pupd = STM32_GPIO_PUPD_NO, 27 .af = STM32_GPIO_AF0 28 }; 29 30 const struct stm32_gpio_ctl gpio_ctl_usart = { 31 .mode = STM32_GPIO_MODE_AF, 32 .otype = STM32_GPIO_OTYPE_PP, 33 .speed = STM32_GPIO_SPEED_50M, 34 .pupd = STM32_GPIO_PUPD_UP, 35 .af = STM32_GPIO_AF7 36 }; 37 38 const struct stm32_gpio_ctl gpio_ctl_fmc = { 39 .mode = STM32_GPIO_MODE_AF, 40 .otype = STM32_GPIO_OTYPE_PP, 41 .speed = STM32_GPIO_SPEED_100M, 42 .pupd = STM32_GPIO_PUPD_NO, 43 .af = STM32_GPIO_AF12 44 }; 45 46 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { 47 /* Chip is LQFP144, see DM00077036.pdf for details */ 48 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ 49 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ 50 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ 51 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ 52 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ 53 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ 54 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ 55 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ 56 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ 57 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ 58 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ 59 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ 60 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ 61 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ 62 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ 63 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ 64 65 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ 66 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ 67 68 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ 69 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ 70 71 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ 72 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ 73 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ 74 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ 75 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ 76 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ 77 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ 78 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ 79 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ 80 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ 81 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ 82 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ 83 84 {STM32_GPIO_PORT_H, STM32_GPIO_PIN_3}, /* 136, SDRAM_NE */ 85 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ 86 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ 87 {STM32_GPIO_PORT_H, STM32_GPIO_PIN_5}, /* 26, SDRAM_NWE */ 88 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_3}, /* 135, SDRAM_CKE */ 89 90 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ 91 }; 92 93 static int fmc_setup_gpio(void) 94 { 95 int rv = 0; 96 int i; 97 98 clock_setup(GPIO_B_CLOCK_CFG); 99 clock_setup(GPIO_C_CLOCK_CFG); 100 clock_setup(GPIO_D_CLOCK_CFG); 101 clock_setup(GPIO_E_CLOCK_CFG); 102 clock_setup(GPIO_F_CLOCK_CFG); 103 clock_setup(GPIO_G_CLOCK_CFG); 104 clock_setup(GPIO_H_CLOCK_CFG); 105 106 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { 107 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], 108 &gpio_ctl_fmc); 109 if (rv) 110 goto out; 111 } 112 113 out: 114 return rv; 115 } 116 117 /* 118 * STM32 RCC FMC specific definitions 119 */ 120 #define RCC_ENR_FMC (1 << 0) /* FMC module clock */ 121 122 static inline u32 _ns2clk(u32 ns, u32 freq) 123 { 124 u32 tmp = freq/1000000; 125 return (tmp * ns) / 1000; 126 } 127 128 #define NS2CLK(ns) (_ns2clk(ns, freq)) 129 130 /* 131 * Following are timings for IS42S16400J, from corresponding datasheet 132 */ 133 #define SDRAM_CAS 3 /* 3 cycles */ 134 #define SDRAM_NB 1 /* Number of banks */ 135 #define SDRAM_MWID 1 /* 16 bit memory */ 136 137 #define SDRAM_NR 0x1 /* 12-bit row */ 138 #define SDRAM_NC 0x0 /* 8-bit col */ 139 #define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ 140 #define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ 141 142 #define SDRAM_TRRD NS2CLK(12) 143 #define SDRAM_TRCD NS2CLK(18) 144 #define SDRAM_TRP NS2CLK(18) 145 #define SDRAM_TRAS NS2CLK(42) 146 #define SDRAM_TRC NS2CLK(60) 147 #define SDRAM_TRFC NS2CLK(60) 148 #define SDRAM_TCDL (1 - 1) 149 #define SDRAM_TRDL NS2CLK(12) 150 #define SDRAM_TBDL (1 - 1) 151 #define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) 152 #define SDRAM_TCCD (1 - 1) 153 154 #define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */ 155 #define SDRAM_TMRD 1 /* Page 10, Mode Register Set */ 156 157 158 /* Last data in to row precharge, need also comply ineq on page 1648 */ 159 #define SDRAM_TWR max(\ 160 (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \ 161 (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\ 162 ) 163 164 165 #define SDRAM_MODE_BL_SHIFT 0 166 #define SDRAM_MODE_CAS_SHIFT 4 167 #define SDRAM_MODE_BL 0 168 #define SDRAM_MODE_CAS SDRAM_CAS 169 170 int dram_init(void) 171 { 172 u32 freq; 173 int rv; 174 175 rv = fmc_setup_gpio(); 176 if (rv) 177 return rv; 178 179 setbits_le32(RCC_BASE + RCC_AHB3ENR, RCC_ENR_FMC); 180 181 /* 182 * Get frequency for NS2CLK calculation. 183 */ 184 freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; 185 186 writel( 187 CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 188 | SDRAM_CAS << FMC_SDCR_CAS_SHIFT 189 | SDRAM_NB << FMC_SDCR_NB_SHIFT 190 | SDRAM_MWID << FMC_SDCR_MWID_SHIFT 191 | SDRAM_NR << FMC_SDCR_NR_SHIFT 192 | SDRAM_NC << FMC_SDCR_NC_SHIFT 193 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 194 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 195 &STM32_SDRAM_FMC->sdcr1); 196 197 writel( 198 SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT 199 | SDRAM_TRP << FMC_SDTR_TRP_SHIFT 200 | SDRAM_TWR << FMC_SDTR_TWR_SHIFT 201 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT 202 | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT 203 | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT 204 | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, 205 &STM32_SDRAM_FMC->sdtr1); 206 207 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, 208 &STM32_SDRAM_FMC->sdcmr); 209 210 udelay(200); /* 200 us delay, page 10, "Power-Up" */ 211 FMC_BUSY_WAIT(); 212 213 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, 214 &STM32_SDRAM_FMC->sdcmr); 215 216 udelay(100); 217 FMC_BUSY_WAIT(); 218 219 writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH 220 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); 221 222 udelay(100); 223 FMC_BUSY_WAIT(); 224 225 writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 226 | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) 227 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 228 &STM32_SDRAM_FMC->sdcmr); 229 230 udelay(100); 231 232 FMC_BUSY_WAIT(); 233 234 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, 235 &STM32_SDRAM_FMC->sdcmr); 236 237 FMC_BUSY_WAIT(); 238 239 /* Refresh timer */ 240 writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); 241 242 /* 243 * Fill in global info with description of SRAM configuration 244 */ 245 gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; 246 gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; 247 248 gd->ram_size = CONFIG_SYS_RAM_SIZE; 249 250 return rv; 251 } 252 253 static const struct stm32_gpio_dsc usart_gpio[] = { 254 {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */ 255 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_7}, /* RX */ 256 }; 257 258 int uart_setup_gpio(void) 259 { 260 int i; 261 int rv = 0; 262 263 clock_setup(GPIO_A_CLOCK_CFG); 264 clock_setup(GPIO_B_CLOCK_CFG); 265 for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { 266 rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); 267 if (rv) 268 goto out; 269 } 270 271 out: 272 return rv; 273 } 274 275 static const struct stm32x7_serial_platdata serial_platdata = { 276 .base = (struct stm32_usart *)USART1_BASE, 277 .clock = CONFIG_SYS_CLK_FREQ, 278 }; 279 280 U_BOOT_DEVICE(stm32x7_serials) = { 281 .name = "serial_stm32x7", 282 .platdata = &serial_platdata, 283 }; 284 285 u32 get_board_rev(void) 286 { 287 return 0; 288 } 289 290 int board_early_init_f(void) 291 { 292 int res; 293 294 res = uart_setup_gpio(); 295 clock_setup(USART1_CLOCK_CFG); 296 if (res) 297 return res; 298 299 return 0; 300 } 301 302 int board_init(void) 303 { 304 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 305 306 return 0; 307 } 308