1 /* 2 * (C) Copyright 2016 3 * Vikas Manocha, <vikas.manocha@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <ram.h> 11 #include <asm/io.h> 12 #include <asm/armv7m.h> 13 #include <asm/arch/stm32.h> 14 #include <asm/arch/gpio.h> 15 #include <dm/platdata.h> 16 #include <dm/platform_data/serial_stm32x7.h> 17 #include <asm/arch/stm32_periph.h> 18 #include <asm/arch/stm32_defs.h> 19 #include <asm/arch/syscfg.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 const struct stm32_gpio_ctl gpio_ctl_gpout = { 24 .mode = STM32_GPIO_MODE_OUT, 25 .otype = STM32_GPIO_OTYPE_PP, 26 .speed = STM32_GPIO_SPEED_50M, 27 .pupd = STM32_GPIO_PUPD_NO, 28 .af = STM32_GPIO_AF0 29 }; 30 31 static int fmc_setup_gpio(void) 32 { 33 clock_setup(GPIO_B_CLOCK_CFG); 34 clock_setup(GPIO_C_CLOCK_CFG); 35 clock_setup(GPIO_D_CLOCK_CFG); 36 clock_setup(GPIO_E_CLOCK_CFG); 37 clock_setup(GPIO_F_CLOCK_CFG); 38 clock_setup(GPIO_G_CLOCK_CFG); 39 clock_setup(GPIO_H_CLOCK_CFG); 40 41 return 0; 42 } 43 44 int dram_init(void) 45 { 46 struct udevice *dev; 47 struct ram_info ram; 48 int rv; 49 50 rv = fmc_setup_gpio(); 51 if (rv) 52 return rv; 53 54 rv = uclass_get_device(UCLASS_RAM, 0, &dev); 55 if (rv) { 56 debug("DRAM init failed: %d\n", rv); 57 return rv; 58 } 59 rv = ram_get_info(dev, &ram); 60 if (rv) { 61 debug("Cannot get DRAM size: %d\n", rv); 62 return rv; 63 } 64 debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); 65 gd->ram_size = ram.size; 66 67 /* 68 * Fill in global info with description of SRAM configuration 69 */ 70 gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; 71 gd->bd->bi_dram[0].size = ram.size; 72 73 return rv; 74 } 75 76 int uart_setup_gpio(void) 77 { 78 clock_setup(GPIO_A_CLOCK_CFG); 79 clock_setup(GPIO_B_CLOCK_CFG); 80 return 0; 81 } 82 83 #ifdef CONFIG_ETH_DESIGNWARE 84 85 static int stmmac_setup(void) 86 { 87 clock_setup(SYSCFG_CLOCK_CFG); 88 /* Set >RMII mode */ 89 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; 90 91 clock_setup(GPIO_A_CLOCK_CFG); 92 clock_setup(GPIO_C_CLOCK_CFG); 93 clock_setup(GPIO_G_CLOCK_CFG); 94 clock_setup(STMMAC_CLOCK_CFG); 95 96 return 0; 97 } 98 #endif 99 100 #ifdef CONFIG_STM32_QSPI 101 102 static int qspi_setup(void) 103 { 104 clock_setup(GPIO_B_CLOCK_CFG); 105 clock_setup(GPIO_D_CLOCK_CFG); 106 clock_setup(GPIO_E_CLOCK_CFG); 107 return 0; 108 } 109 #endif 110 111 u32 get_board_rev(void) 112 { 113 return 0; 114 } 115 116 int board_early_init_f(void) 117 { 118 int res; 119 120 res = uart_setup_gpio(); 121 if (res) 122 return res; 123 124 #ifdef CONFIG_ETH_DESIGNWARE 125 res = stmmac_setup(); 126 if (res) 127 return res; 128 #endif 129 130 #ifdef CONFIG_STM32_QSPI 131 res = qspi_setup(); 132 if (res) 133 return res; 134 #endif 135 136 return 0; 137 } 138 139 int board_init(void) 140 { 141 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 142 143 return 0; 144 } 145