1 /*
2  * (C) Copyright 2016
3  * Vikas Manocha, <vikas.manocha@st.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/armv7m.h>
11 #include <asm/arch/stm32.h>
12 #include <asm/arch/gpio.h>
13 #include <asm/arch/fmc.h>
14 #include <dm/platdata.h>
15 #include <dm/platform_data/serial_stm32x7.h>
16 #include <asm/arch/stm32_periph.h>
17 #include <asm/arch/stm32_defs.h>
18 #include <asm/arch/syscfg.h>
19 
20 DECLARE_GLOBAL_DATA_PTR;
21 
22 const struct stm32_gpio_ctl gpio_ctl_gpout = {
23 	.mode = STM32_GPIO_MODE_OUT,
24 	.otype = STM32_GPIO_OTYPE_PP,
25 	.speed = STM32_GPIO_SPEED_50M,
26 	.pupd = STM32_GPIO_PUPD_NO,
27 	.af = STM32_GPIO_AF0
28 };
29 
30 const struct stm32_gpio_ctl gpio_ctl_fmc = {
31 	.mode = STM32_GPIO_MODE_AF,
32 	.otype = STM32_GPIO_OTYPE_PP,
33 	.speed = STM32_GPIO_SPEED_100M,
34 	.pupd = STM32_GPIO_PUPD_NO,
35 	.af = STM32_GPIO_AF12
36 };
37 
38 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
39 	/* Chip is LQFP144, see DM00077036.pdf for details */
40 	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_10},	/* 79, FMC_D15 */
41 	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_9},	/* 78, FMC_D14 */
42 	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_8},	/* 77, FMC_D13 */
43 	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_15},	/* 68, FMC_D12 */
44 	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_14},	/* 67, FMC_D11 */
45 	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_13},	/* 66, FMC_D10 */
46 	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_12},	/* 65, FMC_D9 */
47 	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_11},	/* 64, FMC_D8 */
48 	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_10},	/* 63, FMC_D7 */
49 	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_9},	/* 60, FMC_D6 */
50 	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_8},	/* 59, FMC_D5 */
51 	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_7},	/* 58, FMC_D4 */
52 	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_1},	/* 115, FMC_D3 */
53 	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_0},	/* 114, FMC_D2 */
54 	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_15},	/* 86, FMC_D1 */
55 	{STM32_GPIO_PORT_D, STM32_GPIO_PIN_14},	/* 85, FMC_D0 */
56 
57 	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_1},	/* 142, FMC_NBL1 */
58 	{STM32_GPIO_PORT_E, STM32_GPIO_PIN_0},	/* 141, FMC_NBL0 */
59 
60 	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_5},	/* 90, FMC_A15, BA1 */
61 	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_4},	/* 89, FMC_A14, BA0 */
62 
63 	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_1},	/* 57, FMC_A11 */
64 	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_0},	/* 56, FMC_A10 */
65 	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_15},	/* 55, FMC_A9 */
66 	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_14},	/* 54, FMC_A8 */
67 	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_13},	/* 53, FMC_A7 */
68 	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_12},	/* 50, FMC_A6 */
69 	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_5},	/* 15, FMC_A5 */
70 	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_4},	/* 14, FMC_A4 */
71 	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_3},	/* 13, FMC_A3 */
72 	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_2},	/* 12, FMC_A2 */
73 	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_1},	/* 11, FMC_A1 */
74 	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_0},	/* 10, FMC_A0 */
75 
76 	{STM32_GPIO_PORT_H, STM32_GPIO_PIN_3},	/* 136, SDRAM_NE */
77 	{STM32_GPIO_PORT_F, STM32_GPIO_PIN_11},	/* 49, SDRAM_NRAS */
78 	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_15},	/* 132, SDRAM_NCAS */
79 	{STM32_GPIO_PORT_H, STM32_GPIO_PIN_5},	/* 26, SDRAM_NWE */
80 	{STM32_GPIO_PORT_C, STM32_GPIO_PIN_3},	/* 135, SDRAM_CKE */
81 
82 	{STM32_GPIO_PORT_G, STM32_GPIO_PIN_8},	/* 93, SDRAM_CLK */
83 };
84 
85 static int fmc_setup_gpio(void)
86 {
87 	int rv = 0;
88 	int i;
89 
90 	clock_setup(GPIO_B_CLOCK_CFG);
91 	clock_setup(GPIO_C_CLOCK_CFG);
92 	clock_setup(GPIO_D_CLOCK_CFG);
93 	clock_setup(GPIO_E_CLOCK_CFG);
94 	clock_setup(GPIO_F_CLOCK_CFG);
95 	clock_setup(GPIO_G_CLOCK_CFG);
96 	clock_setup(GPIO_H_CLOCK_CFG);
97 
98 	for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
99 		rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
100 				&gpio_ctl_fmc);
101 		if (rv)
102 			goto out;
103 	}
104 
105 out:
106 	return rv;
107 }
108 
109 static inline u32 _ns2clk(u32 ns, u32 freq)
110 {
111 	u32 tmp = freq/1000000;
112 	return (tmp * ns) / 1000;
113 }
114 
115 #define NS2CLK(ns) (_ns2clk(ns, freq))
116 
117 /*
118  * Following are timings for IS42S16400J, from corresponding datasheet
119  */
120 #define SDRAM_CAS	3	/* 3 cycles */
121 #define SDRAM_NB	1	/* Number of banks */
122 #define SDRAM_MWID	1	/* 16 bit memory */
123 
124 #define SDRAM_NR	0x1	/* 12-bit row */
125 #define SDRAM_NC	0x0	/* 8-bit col */
126 #define SDRAM_RBURST	0x1	/* Single read requests always as bursts */
127 #define SDRAM_RPIPE	0x0	/* No HCLK clock cycle delay */
128 
129 #define SDRAM_TRRD	NS2CLK(12)
130 #define SDRAM_TRCD	NS2CLK(18)
131 #define SDRAM_TRP	NS2CLK(18)
132 #define SDRAM_TRAS	NS2CLK(42)
133 #define SDRAM_TRC	NS2CLK(60)
134 #define SDRAM_TRFC	NS2CLK(60)
135 #define SDRAM_TCDL	(1 - 1)
136 #define SDRAM_TRDL	NS2CLK(12)
137 #define SDRAM_TBDL	(1 - 1)
138 #define SDRAM_TREF	(NS2CLK(64000000 / 8192) - 20)
139 #define SDRAM_TCCD	(1 - 1)
140 
141 #define SDRAM_TXSR	SDRAM_TRFC	/* Row cycle time after precharge */
142 #define SDRAM_TMRD	1		/* Page 10, Mode Register Set */
143 
144 
145 /* Last data in to row precharge, need also comply ineq on page 1648 */
146 #define SDRAM_TWR	max(\
147 	(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
148 	(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
149 )
150 
151 
152 #define SDRAM_MODE_BL_SHIFT	0
153 #define SDRAM_MODE_CAS_SHIFT	4
154 #define SDRAM_MODE_BL		0
155 #define SDRAM_MODE_CAS		SDRAM_CAS
156 
157 int dram_init(void)
158 {
159 	u32 freq;
160 	int rv;
161 
162 	rv = fmc_setup_gpio();
163 	if (rv)
164 		return rv;
165 
166 	clock_setup(FMC_CLOCK_CFG);
167 
168 	/*
169 	 * Get frequency for NS2CLK calculation.
170 	 */
171 	freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
172 
173 	writel(
174 		CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
175 		| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
176 		| SDRAM_NB << FMC_SDCR_NB_SHIFT
177 		| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
178 		| SDRAM_NR << FMC_SDCR_NR_SHIFT
179 		| SDRAM_NC << FMC_SDCR_NC_SHIFT
180 		| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
181 		| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
182 		&STM32_SDRAM_FMC->sdcr1);
183 
184 	writel(
185 		SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
186 		| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
187 		| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
188 		| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
189 		| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
190 		| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
191 		| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
192 		&STM32_SDRAM_FMC->sdtr1);
193 
194 	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
195 	       &STM32_SDRAM_FMC->sdcmr);
196 
197 	udelay(200);	/* 200 us delay, page 10, "Power-Up" */
198 	FMC_BUSY_WAIT();
199 
200 	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
201 	       &STM32_SDRAM_FMC->sdcmr);
202 
203 	udelay(100);
204 	FMC_BUSY_WAIT();
205 
206 	writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
207 		| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
208 
209 	udelay(100);
210 	FMC_BUSY_WAIT();
211 
212 	writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
213 		| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
214 		<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
215 		&STM32_SDRAM_FMC->sdcmr);
216 
217 	udelay(100);
218 
219 	FMC_BUSY_WAIT();
220 
221 	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
222 	       &STM32_SDRAM_FMC->sdcmr);
223 
224 	FMC_BUSY_WAIT();
225 
226 	/* Refresh timer */
227 	writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
228 
229 	/*
230 	 * Fill in global info with description of SRAM configuration
231 	 */
232 	gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
233 	gd->bd->bi_dram[0].size  = CONFIG_SYS_RAM_SIZE;
234 
235 	gd->ram_size = CONFIG_SYS_RAM_SIZE;
236 
237 	return rv;
238 }
239 
240 int uart_setup_gpio(void)
241 {
242 	clock_setup(GPIO_A_CLOCK_CFG);
243 	clock_setup(GPIO_B_CLOCK_CFG);
244 	return 0;
245 }
246 
247 #ifdef CONFIG_ETH_DESIGNWARE
248 
249 static int stmmac_setup(void)
250 {
251 	clock_setup(SYSCFG_CLOCK_CFG);
252 	/* Set >RMII mode */
253 	STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL;
254 
255 	clock_setup(GPIO_A_CLOCK_CFG);
256 	clock_setup(GPIO_C_CLOCK_CFG);
257 	clock_setup(GPIO_G_CLOCK_CFG);
258 	clock_setup(STMMAC_CLOCK_CFG);
259 
260 	return 0;
261 }
262 #endif
263 
264 #ifdef CONFIG_STM32_QSPI
265 
266 static int qspi_setup(void)
267 {
268 	clock_setup(GPIO_B_CLOCK_CFG);
269 	clock_setup(GPIO_D_CLOCK_CFG);
270 	clock_setup(GPIO_E_CLOCK_CFG);
271 	return 0;
272 }
273 #endif
274 
275 u32 get_board_rev(void)
276 {
277 	return 0;
278 }
279 
280 int board_early_init_f(void)
281 {
282 	int res;
283 
284 	res = uart_setup_gpio();
285 	if (res)
286 		return res;
287 
288 #ifdef CONFIG_ETH_DESIGNWARE
289 	res = stmmac_setup();
290 	if (res)
291 		return res;
292 #endif
293 
294 #ifdef CONFIG_STM32_QSPI
295 	res = qspi_setup();
296 	if (res)
297 		return res;
298 #endif
299 
300 	return 0;
301 }
302 
303 int board_init(void)
304 {
305 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
306 
307 	return 0;
308 }
309