1 /* 2 * (C) Copyright 2011, 2012, 2013 3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4 * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com 5 * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com 6 * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com 7 * 8 * (C) Copyright 2015 9 * Kamil Lulko, <kamil.lulko@gmail.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <asm/io.h> 17 #include <asm/armv7m.h> 18 #include <asm/arch/stm32.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/fmc.h> 21 #include <dm/platform_data/serial_stm32.h> 22 #include <asm/arch/stm32_periph.h> 23 #include <asm/arch/stm32_defs.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 const struct stm32_gpio_ctl gpio_ctl_gpout = { 28 .mode = STM32_GPIO_MODE_OUT, 29 .otype = STM32_GPIO_OTYPE_PP, 30 .speed = STM32_GPIO_SPEED_50M, 31 .pupd = STM32_GPIO_PUPD_NO, 32 .af = STM32_GPIO_AF0 33 }; 34 35 const struct stm32_gpio_ctl gpio_ctl_usart = { 36 .mode = STM32_GPIO_MODE_AF, 37 .otype = STM32_GPIO_OTYPE_PP, 38 .speed = STM32_GPIO_SPEED_50M, 39 .pupd = STM32_GPIO_PUPD_UP, 40 .af = STM32_GPIO_USART 41 }; 42 43 static const struct stm32_gpio_dsc usart_gpio[] = { 44 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */ 45 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */ 46 }; 47 48 int uart_setup_gpio(void) 49 { 50 int i; 51 int rv = 0; 52 53 clock_setup(GPIO_A_CLOCK_CFG); 54 for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { 55 rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); 56 if (rv) 57 goto out; 58 } 59 60 out: 61 return rv; 62 } 63 64 const struct stm32_gpio_ctl gpio_ctl_fmc = { 65 .mode = STM32_GPIO_MODE_AF, 66 .otype = STM32_GPIO_OTYPE_PP, 67 .speed = STM32_GPIO_SPEED_100M, 68 .pupd = STM32_GPIO_PUPD_NO, 69 .af = STM32_GPIO_AF12 70 }; 71 72 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { 73 /* Chip is LQFP144, see DM00077036.pdf for details */ 74 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ 75 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ 76 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ 77 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ 78 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ 79 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ 80 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ 81 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ 82 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ 83 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ 84 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ 85 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ 86 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ 87 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ 88 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ 89 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ 90 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ 91 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ 92 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ 93 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ 94 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ 95 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ 96 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ 97 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ 98 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ 99 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ 100 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ 101 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ 102 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ 103 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ 104 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ 105 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ 106 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */ 107 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ 108 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ 109 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */ 110 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */ 111 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ 112 }; 113 114 static int fmc_setup_gpio(void) 115 { 116 int rv = 0; 117 int i; 118 119 clock_setup(GPIO_B_CLOCK_CFG); 120 clock_setup(GPIO_C_CLOCK_CFG); 121 clock_setup(GPIO_D_CLOCK_CFG); 122 clock_setup(GPIO_E_CLOCK_CFG); 123 clock_setup(GPIO_F_CLOCK_CFG); 124 clock_setup(GPIO_G_CLOCK_CFG); 125 126 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { 127 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], 128 &gpio_ctl_fmc); 129 if (rv) 130 goto out; 131 } 132 133 out: 134 return rv; 135 } 136 137 /* 138 * STM32 RCC FMC specific definitions 139 */ 140 #define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */ 141 142 static inline u32 _ns2clk(u32 ns, u32 freq) 143 { 144 u32 tmp = freq/1000000; 145 return (tmp * ns) / 1000; 146 } 147 148 #define NS2CLK(ns) (_ns2clk(ns, freq)) 149 150 /* 151 * Following are timings for IS42S16400J, from corresponding datasheet 152 */ 153 #define SDRAM_CAS 3 /* 3 cycles */ 154 #define SDRAM_NB 1 /* Number of banks */ 155 #define SDRAM_MWID 1 /* 16 bit memory */ 156 157 #define SDRAM_NR 0x1 /* 12-bit row */ 158 #define SDRAM_NC 0x0 /* 8-bit col */ 159 #define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ 160 #define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ 161 162 #define SDRAM_TRRD (NS2CLK(14) - 1) 163 #define SDRAM_TRCD (NS2CLK(15) - 1) 164 #define SDRAM_TRP (NS2CLK(15) - 1) 165 #define SDRAM_TRAS (NS2CLK(42) - 1) 166 #define SDRAM_TRC (NS2CLK(63) - 1) 167 #define SDRAM_TRFC (NS2CLK(63) - 1) 168 #define SDRAM_TCDL (1 - 1) 169 #define SDRAM_TRDL (2 - 1) 170 #define SDRAM_TBDL (1 - 1) 171 #define SDRAM_TREF 1386 172 #define SDRAM_TCCD (1 - 1) 173 174 #define SDRAM_TXSR (NS2CLK(70) - 1)/* Row cycle time after precharge */ 175 #define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */ 176 177 /* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */ 178 #define SDRAM_TWR max(\ 179 (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \ 180 (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\ 181 ) 182 183 #define SDRAM_MODE_BL_SHIFT 0 184 #define SDRAM_MODE_CAS_SHIFT 4 185 #define SDRAM_MODE_BL 0 186 #define SDRAM_MODE_CAS SDRAM_CAS 187 188 int dram_init(void) 189 { 190 u32 freq; 191 int rv; 192 193 rv = fmc_setup_gpio(); 194 if (rv) 195 return rv; 196 197 setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC); 198 199 /* 200 * Get frequency for NS2CLK calculation. 201 */ 202 freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; 203 204 writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 205 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 206 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 207 &STM32_SDRAM_FMC->sdcr1); 208 209 writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 210 | SDRAM_CAS << FMC_SDCR_CAS_SHIFT 211 | SDRAM_NB << FMC_SDCR_NB_SHIFT 212 | SDRAM_MWID << FMC_SDCR_MWID_SHIFT 213 | SDRAM_NR << FMC_SDCR_NR_SHIFT 214 | SDRAM_NC << FMC_SDCR_NC_SHIFT 215 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 216 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 217 &STM32_SDRAM_FMC->sdcr2); 218 219 writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT 220 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT, 221 &STM32_SDRAM_FMC->sdtr1); 222 223 writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT 224 | SDRAM_TRP << FMC_SDTR_TRP_SHIFT 225 | SDRAM_TWR << FMC_SDTR_TWR_SHIFT 226 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT 227 | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT 228 | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT 229 | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, 230 &STM32_SDRAM_FMC->sdtr2); 231 232 writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK, 233 &STM32_SDRAM_FMC->sdcmr); 234 235 udelay(200); /* 200 us delay, page 10, "Power-Up" */ 236 FMC_BUSY_WAIT(); 237 238 writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE, 239 &STM32_SDRAM_FMC->sdcmr); 240 241 udelay(100); 242 FMC_BUSY_WAIT(); 243 244 writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH 245 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); 246 247 udelay(100); 248 FMC_BUSY_WAIT(); 249 250 writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 251 | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) 252 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 253 &STM32_SDRAM_FMC->sdcmr); 254 255 udelay(100); 256 257 FMC_BUSY_WAIT(); 258 259 writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL, 260 &STM32_SDRAM_FMC->sdcmr); 261 262 FMC_BUSY_WAIT(); 263 264 /* Refresh timer */ 265 writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); 266 267 /* 268 * Fill in global info with description of SRAM configuration 269 */ 270 gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; 271 gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; 272 273 gd->ram_size = CONFIG_SYS_RAM_SIZE; 274 275 return rv; 276 } 277 278 static const struct stm32_serial_platdata serial_platdata = { 279 .base = (struct stm32_usart *)STM32_USART1_BASE, 280 }; 281 282 U_BOOT_DEVICE(stm32_serials) = { 283 .name = "serial_stm32", 284 .platdata = &serial_platdata, 285 }; 286 287 u32 get_board_rev(void) 288 { 289 return 0; 290 } 291 292 int board_early_init_f(void) 293 { 294 int res; 295 296 res = uart_setup_gpio(); 297 if (res) 298 return res; 299 clock_setup(USART1_CLOCK_CFG); 300 301 return 0; 302 } 303 304 int board_init(void) 305 { 306 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 307 308 return 0; 309 } 310 311 #ifdef CONFIG_MISC_INIT_R 312 int misc_init_r(void) 313 { 314 char serialno[25]; 315 uint32_t u_id_low, u_id_mid, u_id_high; 316 317 if (!getenv("serial#")) { 318 u_id_low = readl(&STM32_U_ID->u_id_low); 319 u_id_mid = readl(&STM32_U_ID->u_id_mid); 320 u_id_high = readl(&STM32_U_ID->u_id_high); 321 sprintf(serialno, "%08x%08x%08x", 322 u_id_high, u_id_mid, u_id_low); 323 setenv("serial#", serialno); 324 } 325 326 return 0; 327 } 328 #endif 329