1 /* 2 * (C) Copyright 2011, 2012, 2013 3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4 * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com 5 * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com 6 * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com 7 * 8 * (C) Copyright 2015 9 * Kamil Lulko, <kamil.lulko@gmail.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <asm/io.h> 16 #include <asm/armv7m.h> 17 #include <asm/arch/stm32.h> 18 #include <asm/arch/gpio.h> 19 #include <asm/arch/fmc.h> 20 #include <dm/platdata.h> 21 #include <dm/platform_data/serial_stm32.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 const struct stm32_gpio_ctl gpio_ctl_gpout = { 26 .mode = STM32_GPIO_MODE_OUT, 27 .otype = STM32_GPIO_OTYPE_PP, 28 .speed = STM32_GPIO_SPEED_50M, 29 .pupd = STM32_GPIO_PUPD_NO, 30 .af = STM32_GPIO_AF0 31 }; 32 33 const struct stm32_gpio_ctl gpio_ctl_usart = { 34 .mode = STM32_GPIO_MODE_AF, 35 .otype = STM32_GPIO_OTYPE_PP, 36 .speed = STM32_GPIO_SPEED_50M, 37 .pupd = STM32_GPIO_PUPD_UP, 38 .af = STM32_GPIO_USART 39 }; 40 41 static const struct stm32_gpio_dsc usart_gpio[] = { 42 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */ 43 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */ 44 }; 45 46 int uart_setup_gpio(void) 47 { 48 int i; 49 int rv = 0; 50 51 for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { 52 rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); 53 if (rv) 54 goto out; 55 } 56 57 out: 58 return rv; 59 } 60 61 const struct stm32_gpio_ctl gpio_ctl_fmc = { 62 .mode = STM32_GPIO_MODE_AF, 63 .otype = STM32_GPIO_OTYPE_PP, 64 .speed = STM32_GPIO_SPEED_100M, 65 .pupd = STM32_GPIO_PUPD_NO, 66 .af = STM32_GPIO_AF12 67 }; 68 69 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { 70 /* Chip is LQFP144, see DM00077036.pdf for details */ 71 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ 72 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ 73 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ 74 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ 75 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ 76 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ 77 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ 78 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ 79 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ 80 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ 81 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ 82 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ 83 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ 84 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ 85 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ 86 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ 87 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ 88 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ 89 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ 90 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ 91 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ 92 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ 93 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ 94 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ 95 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ 96 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ 97 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ 98 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ 99 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ 100 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ 101 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ 102 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ 103 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */ 104 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ 105 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ 106 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */ 107 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */ 108 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ 109 }; 110 111 static int fmc_setup_gpio(void) 112 { 113 int rv = 0; 114 int i; 115 116 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { 117 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], 118 &gpio_ctl_fmc); 119 if (rv) 120 goto out; 121 } 122 123 out: 124 return rv; 125 } 126 127 /* 128 * STM32 RCC FMC specific definitions 129 */ 130 #define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */ 131 132 static inline u32 _ns2clk(u32 ns, u32 freq) 133 { 134 u32 tmp = freq/1000000; 135 return (tmp * ns) / 1000; 136 } 137 138 #define NS2CLK(ns) (_ns2clk(ns, freq)) 139 140 /* 141 * Following are timings for IS42S16400J, from corresponding datasheet 142 */ 143 #define SDRAM_CAS 3 /* 3 cycles */ 144 #define SDRAM_NB 1 /* Number of banks */ 145 #define SDRAM_MWID 1 /* 16 bit memory */ 146 147 #define SDRAM_NR 0x1 /* 12-bit row */ 148 #define SDRAM_NC 0x0 /* 8-bit col */ 149 #define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ 150 #define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ 151 152 #define SDRAM_TRRD (NS2CLK(14) - 1) 153 #define SDRAM_TRCD (NS2CLK(15) - 1) 154 #define SDRAM_TRP (NS2CLK(15) - 1) 155 #define SDRAM_TRAS (NS2CLK(42) - 1) 156 #define SDRAM_TRC (NS2CLK(63) - 1) 157 #define SDRAM_TRFC (NS2CLK(63) - 1) 158 #define SDRAM_TCDL (1 - 1) 159 #define SDRAM_TRDL (2 - 1) 160 #define SDRAM_TBDL (1 - 1) 161 #define SDRAM_TREF 1386 162 #define SDRAM_TCCD (1 - 1) 163 164 #define SDRAM_TXSR (NS2CLK(70) - 1)/* Row cycle time after precharge */ 165 #define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */ 166 167 /* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */ 168 #define SDRAM_TWR max(\ 169 (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \ 170 (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\ 171 ) 172 173 #define SDRAM_MODE_BL_SHIFT 0 174 #define SDRAM_MODE_CAS_SHIFT 4 175 #define SDRAM_MODE_BL 0 176 #define SDRAM_MODE_CAS SDRAM_CAS 177 178 int dram_init(void) 179 { 180 u32 freq; 181 int rv; 182 183 rv = fmc_setup_gpio(); 184 if (rv) 185 return rv; 186 187 setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC); 188 189 /* 190 * Get frequency for NS2CLK calculation. 191 */ 192 freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; 193 194 writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 195 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 196 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 197 &STM32_SDRAM_FMC->sdcr1); 198 199 writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 200 | SDRAM_CAS << FMC_SDCR_CAS_SHIFT 201 | SDRAM_NB << FMC_SDCR_NB_SHIFT 202 | SDRAM_MWID << FMC_SDCR_MWID_SHIFT 203 | SDRAM_NR << FMC_SDCR_NR_SHIFT 204 | SDRAM_NC << FMC_SDCR_NC_SHIFT 205 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 206 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 207 &STM32_SDRAM_FMC->sdcr2); 208 209 writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT 210 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT, 211 &STM32_SDRAM_FMC->sdtr1); 212 213 writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT 214 | SDRAM_TRP << FMC_SDTR_TRP_SHIFT 215 | SDRAM_TWR << FMC_SDTR_TWR_SHIFT 216 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT 217 | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT 218 | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT 219 | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, 220 &STM32_SDRAM_FMC->sdtr2); 221 222 writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK, 223 &STM32_SDRAM_FMC->sdcmr); 224 225 udelay(200); /* 200 us delay, page 10, "Power-Up" */ 226 FMC_BUSY_WAIT(); 227 228 writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE, 229 &STM32_SDRAM_FMC->sdcmr); 230 231 udelay(100); 232 FMC_BUSY_WAIT(); 233 234 writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH 235 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); 236 237 udelay(100); 238 FMC_BUSY_WAIT(); 239 240 writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 241 | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) 242 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 243 &STM32_SDRAM_FMC->sdcmr); 244 245 udelay(100); 246 247 FMC_BUSY_WAIT(); 248 249 writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL, 250 &STM32_SDRAM_FMC->sdcmr); 251 252 FMC_BUSY_WAIT(); 253 254 /* Refresh timer */ 255 writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); 256 257 /* 258 * Fill in global info with description of SRAM configuration 259 */ 260 gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; 261 gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; 262 263 gd->ram_size = CONFIG_SYS_RAM_SIZE; 264 265 return rv; 266 } 267 268 static const struct stm32_serial_platdata serial_platdata = { 269 .base = (struct stm32_usart *)STM32_USART1_BASE, 270 }; 271 272 U_BOOT_DEVICE(stm32_serials) = { 273 .name = "serial_stm32", 274 .platdata = &serial_platdata, 275 }; 276 277 u32 get_board_rev(void) 278 { 279 return 0; 280 } 281 282 int board_early_init_f(void) 283 { 284 int res; 285 286 res = uart_setup_gpio(); 287 if (res) 288 return res; 289 290 return 0; 291 } 292 293 int board_init(void) 294 { 295 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 296 297 return 0; 298 } 299 300 #ifdef CONFIG_MISC_INIT_R 301 int misc_init_r(void) 302 { 303 char serialno[25]; 304 uint32_t u_id_low, u_id_mid, u_id_high; 305 306 if (!getenv("serial#")) { 307 u_id_low = readl(&STM32_U_ID->u_id_low); 308 u_id_mid = readl(&STM32_U_ID->u_id_mid); 309 u_id_high = readl(&STM32_U_ID->u_id_high); 310 sprintf(serialno, "%08x%08x%08x", 311 u_id_high, u_id_mid, u_id_low); 312 setenv("serial#", serialno); 313 } 314 315 return 0; 316 } 317 #endif 318