1 /* 2 * (C) Copyright 2011, 2012, 2013 3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4 * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com 5 * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com 6 * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com 7 * 8 * (C) Copyright 2015 9 * Kamil Lulko, <kamil.lulko@gmail.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 17 #include <asm/io.h> 18 #include <asm/arch/stm32.h> 19 #include <asm/arch/gpio.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 const struct stm32_gpio_ctl gpio_ctl_gpout = { 24 .mode = STM32_GPIO_MODE_OUT, 25 .otype = STM32_GPIO_OTYPE_PP, 26 .speed = STM32_GPIO_SPEED_50M, 27 .pupd = STM32_GPIO_PUPD_NO, 28 .af = STM32_GPIO_AF0 29 }; 30 31 const struct stm32_gpio_ctl gpio_ctl_usart = { 32 .mode = STM32_GPIO_MODE_AF, 33 .otype = STM32_GPIO_OTYPE_PP, 34 .speed = STM32_GPIO_SPEED_50M, 35 .pupd = STM32_GPIO_PUPD_UP, 36 .af = STM32_GPIO_USART 37 }; 38 39 static const struct stm32_gpio_dsc usart_gpio[] = { 40 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */ 41 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */ 42 }; 43 44 int uart_setup_gpio(void) 45 { 46 int i; 47 int rv = 0; 48 49 for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { 50 rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); 51 if (rv) 52 goto out; 53 } 54 55 out: 56 return rv; 57 } 58 59 const struct stm32_gpio_ctl gpio_ctl_fmc = { 60 .mode = STM32_GPIO_MODE_AF, 61 .otype = STM32_GPIO_OTYPE_PP, 62 .speed = STM32_GPIO_SPEED_100M, 63 .pupd = STM32_GPIO_PUPD_NO, 64 .af = STM32_GPIO_AF12 65 }; 66 67 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { 68 /* Chip is LQFP144, see DM00077036.pdf for details */ 69 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ 70 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ 71 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ 72 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ 73 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ 74 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ 75 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ 76 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ 77 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ 78 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ 79 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ 80 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ 81 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ 82 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ 83 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ 84 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ 85 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ 86 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ 87 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ 88 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ 89 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ 90 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ 91 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ 92 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ 93 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ 94 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ 95 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ 96 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ 97 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ 98 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ 99 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ 100 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ 101 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */ 102 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ 103 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ 104 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */ 105 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */ 106 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ 107 }; 108 109 static int fmc_setup_gpio(void) 110 { 111 int rv = 0; 112 int i; 113 114 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { 115 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], 116 &gpio_ctl_fmc); 117 if (rv) 118 goto out; 119 } 120 121 out: 122 return rv; 123 } 124 125 int dram_init(void) 126 { 127 int rv; 128 struct udevice *dev; 129 130 rv = fmc_setup_gpio(); 131 if (rv) 132 return rv; 133 rv = uclass_get_device(UCLASS_RAM, 0, &dev); 134 if (rv) { 135 debug("DRAM init failed: %d\n", rv); 136 return rv; 137 } 138 139 if (fdtdec_setup_memory_size() != 0) 140 rv = -EINVAL; 141 142 return rv; 143 } 144 145 int dram_init_banksize(void) 146 { 147 fdtdec_setup_memory_banksize(); 148 149 return 0; 150 } 151 152 u32 get_board_rev(void) 153 { 154 return 0; 155 } 156 157 int board_early_init_f(void) 158 { 159 int res; 160 161 res = uart_setup_gpio(); 162 if (res) 163 return res; 164 return 0; 165 } 166 167 int board_init(void) 168 { 169 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 170 171 return 0; 172 } 173 174 #ifdef CONFIG_MISC_INIT_R 175 int misc_init_r(void) 176 { 177 char serialno[25]; 178 uint32_t u_id_low, u_id_mid, u_id_high; 179 180 if (!env_get("serial#")) { 181 u_id_low = readl(&STM32_U_ID->u_id_low); 182 u_id_mid = readl(&STM32_U_ID->u_id_mid); 183 u_id_high = readl(&STM32_U_ID->u_id_high); 184 sprintf(serialno, "%08x%08x%08x", 185 u_id_high, u_id_mid, u_id_low); 186 env_set("serial#", serialno); 187 } 188 189 return 0; 190 } 191 #endif 192