1 /* 2 * (C) Copyright 2011, 2012, 2013 3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4 * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com 5 * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com 6 * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com 7 * 8 * (C) Copyright 2015 9 * Kamil Lulko, <kamil.lulko@gmail.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <stm32_rcc.h> 17 #include <asm/io.h> 18 #include <asm/armv7m.h> 19 #include <asm/arch/stm32.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/arch/fmc.h> 22 #include <dm/platform_data/serial_stm32.h> 23 #include <asm/arch/stm32_periph.h> 24 #include <asm/arch/stm32_defs.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 const struct stm32_gpio_ctl gpio_ctl_gpout = { 29 .mode = STM32_GPIO_MODE_OUT, 30 .otype = STM32_GPIO_OTYPE_PP, 31 .speed = STM32_GPIO_SPEED_50M, 32 .pupd = STM32_GPIO_PUPD_NO, 33 .af = STM32_GPIO_AF0 34 }; 35 36 const struct stm32_gpio_ctl gpio_ctl_usart = { 37 .mode = STM32_GPIO_MODE_AF, 38 .otype = STM32_GPIO_OTYPE_PP, 39 .speed = STM32_GPIO_SPEED_50M, 40 .pupd = STM32_GPIO_PUPD_UP, 41 .af = STM32_GPIO_USART 42 }; 43 44 static const struct stm32_gpio_dsc usart_gpio[] = { 45 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */ 46 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */ 47 }; 48 49 int uart_setup_gpio(void) 50 { 51 int i; 52 int rv = 0; 53 54 clock_setup(GPIO_A_CLOCK_CFG); 55 for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { 56 rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); 57 if (rv) 58 goto out; 59 } 60 61 out: 62 return rv; 63 } 64 65 const struct stm32_gpio_ctl gpio_ctl_fmc = { 66 .mode = STM32_GPIO_MODE_AF, 67 .otype = STM32_GPIO_OTYPE_PP, 68 .speed = STM32_GPIO_SPEED_100M, 69 .pupd = STM32_GPIO_PUPD_NO, 70 .af = STM32_GPIO_AF12 71 }; 72 73 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { 74 /* Chip is LQFP144, see DM00077036.pdf for details */ 75 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ 76 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ 77 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ 78 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ 79 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ 80 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ 81 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ 82 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ 83 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ 84 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ 85 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ 86 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ 87 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ 88 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ 89 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ 90 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ 91 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ 92 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ 93 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ 94 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ 95 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ 96 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ 97 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ 98 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ 99 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ 100 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ 101 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ 102 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ 103 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ 104 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ 105 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ 106 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ 107 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */ 108 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ 109 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ 110 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */ 111 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */ 112 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ 113 }; 114 115 static int fmc_setup_gpio(void) 116 { 117 int rv = 0; 118 int i; 119 120 clock_setup(GPIO_B_CLOCK_CFG); 121 clock_setup(GPIO_C_CLOCK_CFG); 122 clock_setup(GPIO_D_CLOCK_CFG); 123 clock_setup(GPIO_E_CLOCK_CFG); 124 clock_setup(GPIO_F_CLOCK_CFG); 125 clock_setup(GPIO_G_CLOCK_CFG); 126 127 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { 128 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], 129 &gpio_ctl_fmc); 130 if (rv) 131 goto out; 132 } 133 134 out: 135 return rv; 136 } 137 138 /* 139 * STM32 RCC FMC specific definitions 140 */ 141 #define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */ 142 143 static inline u32 _ns2clk(u32 ns, u32 freq) 144 { 145 u32 tmp = freq/1000000; 146 return (tmp * ns) / 1000; 147 } 148 149 #define NS2CLK(ns) (_ns2clk(ns, freq)) 150 151 /* 152 * Following are timings for IS42S16400J, from corresponding datasheet 153 */ 154 #define SDRAM_CAS 3 /* 3 cycles */ 155 #define SDRAM_NB 1 /* Number of banks */ 156 #define SDRAM_MWID 1 /* 16 bit memory */ 157 158 #define SDRAM_NR 0x1 /* 12-bit row */ 159 #define SDRAM_NC 0x0 /* 8-bit col */ 160 #define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ 161 #define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ 162 163 #define SDRAM_TRRD (NS2CLK(14) - 1) 164 #define SDRAM_TRCD (NS2CLK(15) - 1) 165 #define SDRAM_TRP (NS2CLK(15) - 1) 166 #define SDRAM_TRAS (NS2CLK(42) - 1) 167 #define SDRAM_TRC (NS2CLK(63) - 1) 168 #define SDRAM_TRFC (NS2CLK(63) - 1) 169 #define SDRAM_TCDL (1 - 1) 170 #define SDRAM_TRDL (2 - 1) 171 #define SDRAM_TBDL (1 - 1) 172 #define SDRAM_TREF 1386 173 #define SDRAM_TCCD (1 - 1) 174 175 #define SDRAM_TXSR (NS2CLK(70) - 1)/* Row cycle time after precharge */ 176 #define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */ 177 178 /* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */ 179 #define SDRAM_TWR max(\ 180 (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \ 181 (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\ 182 ) 183 184 #define SDRAM_MODE_BL_SHIFT 0 185 #define SDRAM_MODE_CAS_SHIFT 4 186 #define SDRAM_MODE_BL 0 187 #define SDRAM_MODE_CAS SDRAM_CAS 188 189 int dram_init(void) 190 { 191 u32 freq; 192 int rv; 193 194 rv = fmc_setup_gpio(); 195 if (rv) 196 return rv; 197 198 setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC); 199 200 /* 201 * Get frequency for NS2CLK calculation. 202 */ 203 freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; 204 205 writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 206 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 207 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 208 &STM32_SDRAM_FMC->sdcr1); 209 210 writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 211 | SDRAM_CAS << FMC_SDCR_CAS_SHIFT 212 | SDRAM_NB << FMC_SDCR_NB_SHIFT 213 | SDRAM_MWID << FMC_SDCR_MWID_SHIFT 214 | SDRAM_NR << FMC_SDCR_NR_SHIFT 215 | SDRAM_NC << FMC_SDCR_NC_SHIFT 216 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 217 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 218 &STM32_SDRAM_FMC->sdcr2); 219 220 writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT 221 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT, 222 &STM32_SDRAM_FMC->sdtr1); 223 224 writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT 225 | SDRAM_TRP << FMC_SDTR_TRP_SHIFT 226 | SDRAM_TWR << FMC_SDTR_TWR_SHIFT 227 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT 228 | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT 229 | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT 230 | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, 231 &STM32_SDRAM_FMC->sdtr2); 232 233 writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK, 234 &STM32_SDRAM_FMC->sdcmr); 235 236 udelay(200); /* 200 us delay, page 10, "Power-Up" */ 237 FMC_BUSY_WAIT(); 238 239 writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE, 240 &STM32_SDRAM_FMC->sdcmr); 241 242 udelay(100); 243 FMC_BUSY_WAIT(); 244 245 writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH 246 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); 247 248 udelay(100); 249 FMC_BUSY_WAIT(); 250 251 writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 252 | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) 253 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 254 &STM32_SDRAM_FMC->sdcmr); 255 256 udelay(100); 257 258 FMC_BUSY_WAIT(); 259 260 writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL, 261 &STM32_SDRAM_FMC->sdcmr); 262 263 FMC_BUSY_WAIT(); 264 265 /* Refresh timer */ 266 writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); 267 268 /* 269 * Fill in global info with description of SRAM configuration 270 */ 271 gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; 272 gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; 273 274 gd->ram_size = CONFIG_SYS_RAM_SIZE; 275 276 return rv; 277 } 278 279 static const struct stm32_serial_platdata serial_platdata = { 280 .base = (struct stm32_usart *)STM32_USART1_BASE, 281 }; 282 283 U_BOOT_DEVICE(stm32_serials) = { 284 .name = "serial_stm32", 285 .platdata = &serial_platdata, 286 }; 287 288 u32 get_board_rev(void) 289 { 290 return 0; 291 } 292 293 int board_early_init_f(void) 294 { 295 int res; 296 297 configure_clocks(); 298 299 res = uart_setup_gpio(); 300 if (res) 301 return res; 302 clock_setup(USART1_CLOCK_CFG); 303 304 return 0; 305 } 306 307 int board_init(void) 308 { 309 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 310 311 return 0; 312 } 313 314 #ifdef CONFIG_MISC_INIT_R 315 int misc_init_r(void) 316 { 317 char serialno[25]; 318 uint32_t u_id_low, u_id_mid, u_id_high; 319 320 if (!env_get("serial#")) { 321 u_id_low = readl(&STM32_U_ID->u_id_low); 322 u_id_mid = readl(&STM32_U_ID->u_id_mid); 323 u_id_high = readl(&STM32_U_ID->u_id_high); 324 sprintf(serialno, "%08x%08x%08x", 325 u_id_high, u_id_mid, u_id_low); 326 env_set("serial#", serialno); 327 } 328 329 return 0; 330 } 331 #endif 332