1 /* 2 * (C) Copyright 2011, 2012, 2013 3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4 * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com 5 * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com 6 * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com 7 * 8 * (C) Copyright 2015 9 * Kamil Lulko, <kamil.lulko@gmail.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <stm32_rcc.h> 17 #include <asm/io.h> 18 #include <asm/arch/stm32.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/stm32_periph.h> 21 #include <asm/arch/stm32_defs.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 const struct stm32_gpio_ctl gpio_ctl_gpout = { 26 .mode = STM32_GPIO_MODE_OUT, 27 .otype = STM32_GPIO_OTYPE_PP, 28 .speed = STM32_GPIO_SPEED_50M, 29 .pupd = STM32_GPIO_PUPD_NO, 30 .af = STM32_GPIO_AF0 31 }; 32 33 const struct stm32_gpio_ctl gpio_ctl_usart = { 34 .mode = STM32_GPIO_MODE_AF, 35 .otype = STM32_GPIO_OTYPE_PP, 36 .speed = STM32_GPIO_SPEED_50M, 37 .pupd = STM32_GPIO_PUPD_UP, 38 .af = STM32_GPIO_USART 39 }; 40 41 static const struct stm32_gpio_dsc usart_gpio[] = { 42 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */ 43 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */ 44 }; 45 46 int uart_setup_gpio(void) 47 { 48 int i; 49 int rv = 0; 50 51 clock_setup(GPIO_A_CLOCK_CFG); 52 for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { 53 rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); 54 if (rv) 55 goto out; 56 } 57 58 out: 59 return rv; 60 } 61 62 const struct stm32_gpio_ctl gpio_ctl_fmc = { 63 .mode = STM32_GPIO_MODE_AF, 64 .otype = STM32_GPIO_OTYPE_PP, 65 .speed = STM32_GPIO_SPEED_100M, 66 .pupd = STM32_GPIO_PUPD_NO, 67 .af = STM32_GPIO_AF12 68 }; 69 70 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { 71 /* Chip is LQFP144, see DM00077036.pdf for details */ 72 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ 73 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ 74 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ 75 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ 76 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ 77 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ 78 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ 79 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ 80 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ 81 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ 82 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ 83 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ 84 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ 85 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ 86 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ 87 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ 88 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ 89 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ 90 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ 91 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ 92 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ 93 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ 94 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ 95 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ 96 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ 97 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ 98 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ 99 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ 100 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ 101 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ 102 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ 103 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ 104 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */ 105 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ 106 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ 107 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */ 108 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */ 109 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ 110 }; 111 112 static int fmc_setup_gpio(void) 113 { 114 int rv = 0; 115 int i; 116 117 clock_setup(GPIO_B_CLOCK_CFG); 118 clock_setup(GPIO_C_CLOCK_CFG); 119 clock_setup(GPIO_D_CLOCK_CFG); 120 clock_setup(GPIO_E_CLOCK_CFG); 121 clock_setup(GPIO_F_CLOCK_CFG); 122 clock_setup(GPIO_G_CLOCK_CFG); 123 124 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { 125 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], 126 &gpio_ctl_fmc); 127 if (rv) 128 goto out; 129 } 130 131 out: 132 return rv; 133 } 134 135 /* 136 * STM32 RCC FMC specific definitions 137 */ 138 #define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */ 139 140 int dram_init(void) 141 { 142 int rv; 143 struct udevice *dev; 144 145 rv = fmc_setup_gpio(); 146 if (rv) 147 return rv; 148 149 setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC); 150 151 rv = uclass_get_device(UCLASS_RAM, 0, &dev); 152 if (rv) { 153 debug("DRAM init failed: %d\n", rv); 154 return rv; 155 } 156 157 if (fdtdec_setup_memory_size() != 0) 158 rv = -EINVAL; 159 160 return rv; 161 } 162 163 int dram_init_banksize(void) 164 { 165 fdtdec_setup_memory_banksize(); 166 167 return 0; 168 } 169 170 u32 get_board_rev(void) 171 { 172 return 0; 173 } 174 175 int board_early_init_f(void) 176 { 177 int res; 178 179 configure_clocks(); 180 181 res = uart_setup_gpio(); 182 if (res) 183 return res; 184 clock_setup(USART1_CLOCK_CFG); 185 186 return 0; 187 } 188 189 int board_init(void) 190 { 191 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 192 193 return 0; 194 } 195 196 #ifdef CONFIG_MISC_INIT_R 197 int misc_init_r(void) 198 { 199 char serialno[25]; 200 uint32_t u_id_low, u_id_mid, u_id_high; 201 202 if (!env_get("serial#")) { 203 u_id_low = readl(&STM32_U_ID->u_id_low); 204 u_id_mid = readl(&STM32_U_ID->u_id_mid); 205 u_id_high = readl(&STM32_U_ID->u_id_high); 206 sprintf(serialno, "%08x%08x%08x", 207 u_id_high, u_id_mid, u_id_low); 208 env_set("serial#", serialno); 209 } 210 211 return 0; 212 } 213 #endif 214