1 /* 2 * (C) Copyright 2011, 2012, 2013 3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4 * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com 5 * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com 6 * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com 7 * 8 * (C) Copyright 2015 9 * Kamil Lulko, <rev13@wp.pl> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <asm/io.h> 16 #include <asm/armv7m.h> 17 #include <asm/arch/stm32.h> 18 #include <asm/arch/gpio.h> 19 #include <asm/arch/fmc.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 const struct stm32_gpio_ctl gpio_ctl_gpout = { 24 .mode = STM32_GPIO_MODE_OUT, 25 .otype = STM32_GPIO_OTYPE_PP, 26 .speed = STM32_GPIO_SPEED_50M, 27 .pupd = STM32_GPIO_PUPD_NO, 28 .af = STM32_GPIO_AF0 29 }; 30 31 const struct stm32_gpio_ctl gpio_ctl_usart = { 32 .mode = STM32_GPIO_MODE_AF, 33 .otype = STM32_GPIO_OTYPE_PP, 34 .speed = STM32_GPIO_SPEED_50M, 35 .pupd = STM32_GPIO_PUPD_UP, 36 .af = STM32_GPIO_USART 37 }; 38 39 static const struct stm32_gpio_dsc usart_gpio[] = { 40 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */ 41 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */ 42 }; 43 44 int uart_setup_gpio(void) 45 { 46 int i; 47 int rv = 0; 48 49 for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { 50 rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); 51 if (rv) 52 goto out; 53 } 54 55 out: 56 return rv; 57 } 58 59 const struct stm32_gpio_ctl gpio_ctl_fmc = { 60 .mode = STM32_GPIO_MODE_AF, 61 .otype = STM32_GPIO_OTYPE_PP, 62 .speed = STM32_GPIO_SPEED_100M, 63 .pupd = STM32_GPIO_PUPD_NO, 64 .af = STM32_GPIO_AF12 65 }; 66 67 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { 68 /* Chip is LQFP144, see DM00077036.pdf for details */ 69 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ 70 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ 71 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ 72 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ 73 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ 74 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ 75 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ 76 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ 77 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ 78 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ 79 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ 80 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ 81 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ 82 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ 83 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ 84 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ 85 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ 86 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ 87 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ 88 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ 89 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ 90 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ 91 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ 92 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ 93 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ 94 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ 95 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ 96 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ 97 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ 98 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ 99 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ 100 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ 101 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */ 102 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ 103 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ 104 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */ 105 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */ 106 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ 107 }; 108 109 static int fmc_setup_gpio(void) 110 { 111 int rv = 0; 112 int i; 113 114 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { 115 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], 116 &gpio_ctl_fmc); 117 if (rv) 118 goto out; 119 } 120 121 out: 122 return rv; 123 } 124 125 /* 126 * STM32 RCC FMC specific definitions 127 */ 128 #define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */ 129 130 static inline u32 _ns2clk(u32 ns, u32 freq) 131 { 132 u32 tmp = freq/1000000; 133 return (tmp * ns) / 1000; 134 } 135 136 #define NS2CLK(ns) (_ns2clk(ns, freq)) 137 138 /* 139 * Following are timings for IS42S16400J, from corresponding datasheet 140 */ 141 #define SDRAM_CAS 3 /* 3 cycles */ 142 #define SDRAM_NB 1 /* Number of banks */ 143 #define SDRAM_MWID 1 /* 16 bit memory */ 144 145 #define SDRAM_NR 0x1 /* 12-bit row */ 146 #define SDRAM_NC 0x0 /* 8-bit col */ 147 #define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ 148 #define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ 149 150 #define SDRAM_TRRD (NS2CLK(14) - 1) 151 #define SDRAM_TRCD (NS2CLK(15) - 1) 152 #define SDRAM_TRP (NS2CLK(15) - 1) 153 #define SDRAM_TRAS (NS2CLK(42) - 1) 154 #define SDRAM_TRC (NS2CLK(63) - 1) 155 #define SDRAM_TRFC (NS2CLK(63) - 1) 156 #define SDRAM_TCDL (1 - 1) 157 #define SDRAM_TRDL (2 - 1) 158 #define SDRAM_TBDL (1 - 1) 159 #define SDRAM_TREF 1386 160 #define SDRAM_TCCD (1 - 1) 161 162 #define SDRAM_TXSR (NS2CLK(70) - 1)/* Row cycle time after precharge */ 163 #define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */ 164 165 /* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */ 166 #define SDRAM_TWR max(\ 167 (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \ 168 (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\ 169 ) 170 171 #define SDRAM_MODE_BL_SHIFT 0 172 #define SDRAM_MODE_CAS_SHIFT 4 173 #define SDRAM_MODE_BL 0 174 #define SDRAM_MODE_CAS SDRAM_CAS 175 176 int dram_init(void) 177 { 178 u32 freq; 179 int rv; 180 181 rv = fmc_setup_gpio(); 182 if (rv) 183 return rv; 184 185 setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC); 186 187 /* 188 * Get frequency for NS2CLK calculation. 189 */ 190 freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; 191 192 writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 193 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 194 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 195 &STM32_SDRAM_FMC->sdcr1); 196 197 writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 198 | SDRAM_CAS << FMC_SDCR_CAS_SHIFT 199 | SDRAM_NB << FMC_SDCR_NB_SHIFT 200 | SDRAM_MWID << FMC_SDCR_MWID_SHIFT 201 | SDRAM_NR << FMC_SDCR_NR_SHIFT 202 | SDRAM_NC << FMC_SDCR_NC_SHIFT 203 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 204 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 205 &STM32_SDRAM_FMC->sdcr2); 206 207 writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT 208 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT, 209 &STM32_SDRAM_FMC->sdtr1); 210 211 writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT 212 | SDRAM_TRP << FMC_SDTR_TRP_SHIFT 213 | SDRAM_TWR << FMC_SDTR_TWR_SHIFT 214 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT 215 | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT 216 | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT 217 | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, 218 &STM32_SDRAM_FMC->sdtr2); 219 220 writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK, 221 &STM32_SDRAM_FMC->sdcmr); 222 223 udelay(200); /* 200 us delay, page 10, "Power-Up" */ 224 FMC_BUSY_WAIT(); 225 226 writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE, 227 &STM32_SDRAM_FMC->sdcmr); 228 229 udelay(100); 230 FMC_BUSY_WAIT(); 231 232 writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH 233 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); 234 235 udelay(100); 236 FMC_BUSY_WAIT(); 237 238 writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 239 | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) 240 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 241 &STM32_SDRAM_FMC->sdcmr); 242 243 udelay(100); 244 245 FMC_BUSY_WAIT(); 246 247 writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL, 248 &STM32_SDRAM_FMC->sdcmr); 249 250 FMC_BUSY_WAIT(); 251 252 /* Refresh timer */ 253 writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); 254 255 /* 256 * Fill in global info with description of SRAM configuration 257 */ 258 gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; 259 gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; 260 261 gd->ram_size = CONFIG_SYS_RAM_SIZE; 262 263 return rv; 264 } 265 266 u32 get_board_rev(void) 267 { 268 return 0; 269 } 270 271 int board_early_init_f(void) 272 { 273 int res; 274 275 res = uart_setup_gpio(); 276 if (res) 277 return res; 278 279 return 0; 280 } 281 282 int board_init(void) 283 { 284 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 285 286 return 0; 287 } 288 289 #ifdef CONFIG_MISC_INIT_R 290 int misc_init_r(void) 291 { 292 char serialno[25]; 293 uint32_t u_id_low, u_id_mid, u_id_high; 294 295 if (!getenv("serial#")) { 296 u_id_low = readl(&STM32_U_ID->u_id_low); 297 u_id_mid = readl(&STM32_U_ID->u_id_mid); 298 u_id_high = readl(&STM32_U_ID->u_id_high); 299 sprintf(serialno, "%08x%08x%08x", 300 u_id_high, u_id_mid, u_id_low); 301 setenv("serial#", serialno); 302 } 303 304 return 0; 305 } 306 #endif 307