1*ed09a554Srev13@wp.pl /* 2*ed09a554Srev13@wp.pl * (C) Copyright 2011, 2012, 2013 3*ed09a554Srev13@wp.pl * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4*ed09a554Srev13@wp.pl * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com 5*ed09a554Srev13@wp.pl * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com 6*ed09a554Srev13@wp.pl * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com 7*ed09a554Srev13@wp.pl * 8*ed09a554Srev13@wp.pl * (C) Copyright 2015 9*ed09a554Srev13@wp.pl * Kamil Lulko, <rev13@wp.pl> 10*ed09a554Srev13@wp.pl * 11*ed09a554Srev13@wp.pl * SPDX-License-Identifier: GPL-2.0+ 12*ed09a554Srev13@wp.pl */ 13*ed09a554Srev13@wp.pl 14*ed09a554Srev13@wp.pl #include <common.h> 15*ed09a554Srev13@wp.pl #include <asm/io.h> 16*ed09a554Srev13@wp.pl #include <asm/armv7m.h> 17*ed09a554Srev13@wp.pl #include <asm/arch/stm32.h> 18*ed09a554Srev13@wp.pl #include <asm/arch/gpio.h> 19*ed09a554Srev13@wp.pl #include <asm/arch/fmc.h> 20*ed09a554Srev13@wp.pl 21*ed09a554Srev13@wp.pl DECLARE_GLOBAL_DATA_PTR; 22*ed09a554Srev13@wp.pl 23*ed09a554Srev13@wp.pl const struct stm32_gpio_ctl gpio_ctl_gpout = { 24*ed09a554Srev13@wp.pl .mode = STM32_GPIO_MODE_OUT, 25*ed09a554Srev13@wp.pl .otype = STM32_GPIO_OTYPE_PP, 26*ed09a554Srev13@wp.pl .speed = STM32_GPIO_SPEED_50M, 27*ed09a554Srev13@wp.pl .pupd = STM32_GPIO_PUPD_NO, 28*ed09a554Srev13@wp.pl .af = STM32_GPIO_AF0 29*ed09a554Srev13@wp.pl }; 30*ed09a554Srev13@wp.pl 31*ed09a554Srev13@wp.pl const struct stm32_gpio_ctl gpio_ctl_usart = { 32*ed09a554Srev13@wp.pl .mode = STM32_GPIO_MODE_AF, 33*ed09a554Srev13@wp.pl .otype = STM32_GPIO_OTYPE_PP, 34*ed09a554Srev13@wp.pl .speed = STM32_GPIO_SPEED_50M, 35*ed09a554Srev13@wp.pl .pupd = STM32_GPIO_PUPD_UP, 36*ed09a554Srev13@wp.pl .af = STM32_GPIO_AF7 37*ed09a554Srev13@wp.pl }; 38*ed09a554Srev13@wp.pl 39*ed09a554Srev13@wp.pl static const struct stm32_gpio_dsc usart1_gpio[] = { 40*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */ 41*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_A, STM32_GPIO_PIN_10}, /* RX */ 42*ed09a554Srev13@wp.pl }; 43*ed09a554Srev13@wp.pl 44*ed09a554Srev13@wp.pl int uart1_setup_gpio(void) 45*ed09a554Srev13@wp.pl { 46*ed09a554Srev13@wp.pl int i; 47*ed09a554Srev13@wp.pl int rv = 0; 48*ed09a554Srev13@wp.pl 49*ed09a554Srev13@wp.pl for (i = 0; i < ARRAY_SIZE(usart1_gpio); i++) { 50*ed09a554Srev13@wp.pl rv = stm32_gpio_config(&usart1_gpio[i], &gpio_ctl_usart); 51*ed09a554Srev13@wp.pl if (rv) 52*ed09a554Srev13@wp.pl goto out; 53*ed09a554Srev13@wp.pl } 54*ed09a554Srev13@wp.pl 55*ed09a554Srev13@wp.pl out: 56*ed09a554Srev13@wp.pl return rv; 57*ed09a554Srev13@wp.pl } 58*ed09a554Srev13@wp.pl 59*ed09a554Srev13@wp.pl const struct stm32_gpio_ctl gpio_ctl_fmc = { 60*ed09a554Srev13@wp.pl .mode = STM32_GPIO_MODE_AF, 61*ed09a554Srev13@wp.pl .otype = STM32_GPIO_OTYPE_PP, 62*ed09a554Srev13@wp.pl .speed = STM32_GPIO_SPEED_100M, 63*ed09a554Srev13@wp.pl .pupd = STM32_GPIO_PUPD_NO, 64*ed09a554Srev13@wp.pl .af = STM32_GPIO_AF12 65*ed09a554Srev13@wp.pl }; 66*ed09a554Srev13@wp.pl 67*ed09a554Srev13@wp.pl static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { 68*ed09a554Srev13@wp.pl /* Chip is LQFP144, see DM00077036.pdf for details */ 69*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ 70*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ 71*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ 72*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ 73*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ 74*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ 75*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ 76*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ 77*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ 78*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ 79*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ 80*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ 81*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ 82*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ 83*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ 84*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ 85*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ 86*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ 87*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ 88*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ 89*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ 90*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ 91*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ 92*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ 93*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ 94*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ 95*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ 96*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ 97*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ 98*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ 99*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ 100*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ 101*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */ 102*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ 103*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ 104*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */ 105*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */ 106*ed09a554Srev13@wp.pl {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ 107*ed09a554Srev13@wp.pl }; 108*ed09a554Srev13@wp.pl 109*ed09a554Srev13@wp.pl static int fmc_setup_gpio(void) 110*ed09a554Srev13@wp.pl { 111*ed09a554Srev13@wp.pl int rv = 0; 112*ed09a554Srev13@wp.pl int i; 113*ed09a554Srev13@wp.pl 114*ed09a554Srev13@wp.pl for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { 115*ed09a554Srev13@wp.pl rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], 116*ed09a554Srev13@wp.pl &gpio_ctl_fmc); 117*ed09a554Srev13@wp.pl if (rv) 118*ed09a554Srev13@wp.pl goto out; 119*ed09a554Srev13@wp.pl } 120*ed09a554Srev13@wp.pl 121*ed09a554Srev13@wp.pl out: 122*ed09a554Srev13@wp.pl return rv; 123*ed09a554Srev13@wp.pl } 124*ed09a554Srev13@wp.pl 125*ed09a554Srev13@wp.pl /* 126*ed09a554Srev13@wp.pl * STM32 RCC FMC specific definitions 127*ed09a554Srev13@wp.pl */ 128*ed09a554Srev13@wp.pl #define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */ 129*ed09a554Srev13@wp.pl 130*ed09a554Srev13@wp.pl static inline u32 _ns2clk(u32 ns, u32 freq) 131*ed09a554Srev13@wp.pl { 132*ed09a554Srev13@wp.pl u32 tmp = freq/1000000; 133*ed09a554Srev13@wp.pl return (tmp * ns) / 1000; 134*ed09a554Srev13@wp.pl } 135*ed09a554Srev13@wp.pl 136*ed09a554Srev13@wp.pl #define NS2CLK(ns) (_ns2clk(ns, freq)) 137*ed09a554Srev13@wp.pl 138*ed09a554Srev13@wp.pl /* 139*ed09a554Srev13@wp.pl * Following are timings for IS42S16400J, from corresponding datasheet 140*ed09a554Srev13@wp.pl */ 141*ed09a554Srev13@wp.pl #define SDRAM_CAS 3 /* 3 cycles */ 142*ed09a554Srev13@wp.pl #define SDRAM_NB 1 /* Number of banks */ 143*ed09a554Srev13@wp.pl #define SDRAM_MWID 1 /* 16 bit memory */ 144*ed09a554Srev13@wp.pl 145*ed09a554Srev13@wp.pl #define SDRAM_NR 0x1 /* 12-bit row */ 146*ed09a554Srev13@wp.pl #define SDRAM_NC 0x0 /* 8-bit col */ 147*ed09a554Srev13@wp.pl #define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ 148*ed09a554Srev13@wp.pl #define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ 149*ed09a554Srev13@wp.pl 150*ed09a554Srev13@wp.pl #define SDRAM_TRRD (NS2CLK(14) - 1) 151*ed09a554Srev13@wp.pl #define SDRAM_TRCD (NS2CLK(15) - 1) 152*ed09a554Srev13@wp.pl #define SDRAM_TRP (NS2CLK(15) - 1) 153*ed09a554Srev13@wp.pl #define SDRAM_TRAS (NS2CLK(42) - 1) 154*ed09a554Srev13@wp.pl #define SDRAM_TRC (NS2CLK(63) - 1) 155*ed09a554Srev13@wp.pl #define SDRAM_TRFC (NS2CLK(63) - 1) 156*ed09a554Srev13@wp.pl #define SDRAM_TCDL (1 - 1) 157*ed09a554Srev13@wp.pl #define SDRAM_TRDL (2 - 1) 158*ed09a554Srev13@wp.pl #define SDRAM_TBDL (1 - 1) 159*ed09a554Srev13@wp.pl #define SDRAM_TREF 1386 160*ed09a554Srev13@wp.pl #define SDRAM_TCCD (1 - 1) 161*ed09a554Srev13@wp.pl 162*ed09a554Srev13@wp.pl #define SDRAM_TXSR (NS2CLK(70) - 1)/* Row cycle time after precharge */ 163*ed09a554Srev13@wp.pl #define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */ 164*ed09a554Srev13@wp.pl 165*ed09a554Srev13@wp.pl /* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */ 166*ed09a554Srev13@wp.pl #define SDRAM_TWR max(\ 167*ed09a554Srev13@wp.pl (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \ 168*ed09a554Srev13@wp.pl (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\ 169*ed09a554Srev13@wp.pl ) 170*ed09a554Srev13@wp.pl 171*ed09a554Srev13@wp.pl #define SDRAM_MODE_BL_SHIFT 0 172*ed09a554Srev13@wp.pl #define SDRAM_MODE_CAS_SHIFT 4 173*ed09a554Srev13@wp.pl #define SDRAM_MODE_BL 0 174*ed09a554Srev13@wp.pl #define SDRAM_MODE_CAS SDRAM_CAS 175*ed09a554Srev13@wp.pl 176*ed09a554Srev13@wp.pl int dram_init(void) 177*ed09a554Srev13@wp.pl { 178*ed09a554Srev13@wp.pl u32 freq; 179*ed09a554Srev13@wp.pl int rv; 180*ed09a554Srev13@wp.pl 181*ed09a554Srev13@wp.pl rv = fmc_setup_gpio(); 182*ed09a554Srev13@wp.pl if (rv) 183*ed09a554Srev13@wp.pl return rv; 184*ed09a554Srev13@wp.pl 185*ed09a554Srev13@wp.pl setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC); 186*ed09a554Srev13@wp.pl 187*ed09a554Srev13@wp.pl /* 188*ed09a554Srev13@wp.pl * Get frequency for NS2CLK calculation. 189*ed09a554Srev13@wp.pl */ 190*ed09a554Srev13@wp.pl freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; 191*ed09a554Srev13@wp.pl 192*ed09a554Srev13@wp.pl writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 193*ed09a554Srev13@wp.pl | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 194*ed09a554Srev13@wp.pl | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 195*ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdcr1); 196*ed09a554Srev13@wp.pl 197*ed09a554Srev13@wp.pl writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 198*ed09a554Srev13@wp.pl | SDRAM_CAS << FMC_SDCR_CAS_SHIFT 199*ed09a554Srev13@wp.pl | SDRAM_NB << FMC_SDCR_NB_SHIFT 200*ed09a554Srev13@wp.pl | SDRAM_MWID << FMC_SDCR_MWID_SHIFT 201*ed09a554Srev13@wp.pl | SDRAM_NR << FMC_SDCR_NR_SHIFT 202*ed09a554Srev13@wp.pl | SDRAM_NC << FMC_SDCR_NC_SHIFT 203*ed09a554Srev13@wp.pl | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 204*ed09a554Srev13@wp.pl | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 205*ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdcr2); 206*ed09a554Srev13@wp.pl 207*ed09a554Srev13@wp.pl writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT 208*ed09a554Srev13@wp.pl | SDRAM_TRC << FMC_SDTR_TRC_SHIFT, 209*ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdtr1); 210*ed09a554Srev13@wp.pl 211*ed09a554Srev13@wp.pl writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT 212*ed09a554Srev13@wp.pl | SDRAM_TRP << FMC_SDTR_TRP_SHIFT 213*ed09a554Srev13@wp.pl | SDRAM_TWR << FMC_SDTR_TWR_SHIFT 214*ed09a554Srev13@wp.pl | SDRAM_TRC << FMC_SDTR_TRC_SHIFT 215*ed09a554Srev13@wp.pl | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT 216*ed09a554Srev13@wp.pl | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT 217*ed09a554Srev13@wp.pl | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, 218*ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdtr2); 219*ed09a554Srev13@wp.pl 220*ed09a554Srev13@wp.pl writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK, 221*ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdcmr); 222*ed09a554Srev13@wp.pl 223*ed09a554Srev13@wp.pl udelay(200); /* 200 us delay, page 10, "Power-Up" */ 224*ed09a554Srev13@wp.pl FMC_BUSY_WAIT(); 225*ed09a554Srev13@wp.pl 226*ed09a554Srev13@wp.pl writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE, 227*ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdcmr); 228*ed09a554Srev13@wp.pl 229*ed09a554Srev13@wp.pl udelay(100); 230*ed09a554Srev13@wp.pl FMC_BUSY_WAIT(); 231*ed09a554Srev13@wp.pl 232*ed09a554Srev13@wp.pl writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH 233*ed09a554Srev13@wp.pl | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); 234*ed09a554Srev13@wp.pl 235*ed09a554Srev13@wp.pl udelay(100); 236*ed09a554Srev13@wp.pl FMC_BUSY_WAIT(); 237*ed09a554Srev13@wp.pl 238*ed09a554Srev13@wp.pl writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 239*ed09a554Srev13@wp.pl | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) 240*ed09a554Srev13@wp.pl << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 241*ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdcmr); 242*ed09a554Srev13@wp.pl 243*ed09a554Srev13@wp.pl udelay(100); 244*ed09a554Srev13@wp.pl 245*ed09a554Srev13@wp.pl FMC_BUSY_WAIT(); 246*ed09a554Srev13@wp.pl 247*ed09a554Srev13@wp.pl writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL, 248*ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdcmr); 249*ed09a554Srev13@wp.pl 250*ed09a554Srev13@wp.pl FMC_BUSY_WAIT(); 251*ed09a554Srev13@wp.pl 252*ed09a554Srev13@wp.pl /* Refresh timer */ 253*ed09a554Srev13@wp.pl writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); 254*ed09a554Srev13@wp.pl 255*ed09a554Srev13@wp.pl /* 256*ed09a554Srev13@wp.pl * Fill in global info with description of SRAM configuration 257*ed09a554Srev13@wp.pl */ 258*ed09a554Srev13@wp.pl gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; 259*ed09a554Srev13@wp.pl gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; 260*ed09a554Srev13@wp.pl 261*ed09a554Srev13@wp.pl gd->ram_size = CONFIG_SYS_RAM_SIZE; 262*ed09a554Srev13@wp.pl 263*ed09a554Srev13@wp.pl return rv; 264*ed09a554Srev13@wp.pl } 265*ed09a554Srev13@wp.pl 266*ed09a554Srev13@wp.pl u32 get_board_rev(void) 267*ed09a554Srev13@wp.pl { 268*ed09a554Srev13@wp.pl return 0; 269*ed09a554Srev13@wp.pl } 270*ed09a554Srev13@wp.pl 271*ed09a554Srev13@wp.pl int board_early_init_f(void) 272*ed09a554Srev13@wp.pl { 273*ed09a554Srev13@wp.pl int res; 274*ed09a554Srev13@wp.pl 275*ed09a554Srev13@wp.pl res = uart1_setup_gpio(); 276*ed09a554Srev13@wp.pl if (res) 277*ed09a554Srev13@wp.pl return res; 278*ed09a554Srev13@wp.pl 279*ed09a554Srev13@wp.pl return 0; 280*ed09a554Srev13@wp.pl } 281*ed09a554Srev13@wp.pl 282*ed09a554Srev13@wp.pl int board_init(void) 283*ed09a554Srev13@wp.pl { 284*ed09a554Srev13@wp.pl gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 285*ed09a554Srev13@wp.pl 286*ed09a554Srev13@wp.pl return 0; 287*ed09a554Srev13@wp.pl } 288