1ed09a554Srev13@wp.pl /* 2ed09a554Srev13@wp.pl * (C) Copyright 2011, 2012, 2013 3ed09a554Srev13@wp.pl * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4ed09a554Srev13@wp.pl * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com 5ed09a554Srev13@wp.pl * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com 6ed09a554Srev13@wp.pl * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com 7ed09a554Srev13@wp.pl * 8ed09a554Srev13@wp.pl * (C) Copyright 2015 9ed09a554Srev13@wp.pl * Kamil Lulko, <rev13@wp.pl> 10ed09a554Srev13@wp.pl * 11ed09a554Srev13@wp.pl * SPDX-License-Identifier: GPL-2.0+ 12ed09a554Srev13@wp.pl */ 13ed09a554Srev13@wp.pl 14ed09a554Srev13@wp.pl #include <common.h> 15ed09a554Srev13@wp.pl #include <asm/io.h> 16ed09a554Srev13@wp.pl #include <asm/armv7m.h> 17ed09a554Srev13@wp.pl #include <asm/arch/stm32.h> 18ed09a554Srev13@wp.pl #include <asm/arch/gpio.h> 19ed09a554Srev13@wp.pl #include <asm/arch/fmc.h> 20ed09a554Srev13@wp.pl 21ed09a554Srev13@wp.pl DECLARE_GLOBAL_DATA_PTR; 22ed09a554Srev13@wp.pl 23ed09a554Srev13@wp.pl const struct stm32_gpio_ctl gpio_ctl_gpout = { 24ed09a554Srev13@wp.pl .mode = STM32_GPIO_MODE_OUT, 25ed09a554Srev13@wp.pl .otype = STM32_GPIO_OTYPE_PP, 26ed09a554Srev13@wp.pl .speed = STM32_GPIO_SPEED_50M, 27ed09a554Srev13@wp.pl .pupd = STM32_GPIO_PUPD_NO, 28ed09a554Srev13@wp.pl .af = STM32_GPIO_AF0 29ed09a554Srev13@wp.pl }; 30ed09a554Srev13@wp.pl 31ed09a554Srev13@wp.pl const struct stm32_gpio_ctl gpio_ctl_usart = { 32ed09a554Srev13@wp.pl .mode = STM32_GPIO_MODE_AF, 33ed09a554Srev13@wp.pl .otype = STM32_GPIO_OTYPE_PP, 34ed09a554Srev13@wp.pl .speed = STM32_GPIO_SPEED_50M, 35ed09a554Srev13@wp.pl .pupd = STM32_GPIO_PUPD_UP, 3660570df1Skunhuahuang .af = STM32_GPIO_USART 37ed09a554Srev13@wp.pl }; 38ed09a554Srev13@wp.pl 3960570df1Skunhuahuang static const struct stm32_gpio_dsc usart_gpio[] = { 4060570df1Skunhuahuang {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */ 4160570df1Skunhuahuang {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */ 42ed09a554Srev13@wp.pl }; 43ed09a554Srev13@wp.pl 4460570df1Skunhuahuang int uart_setup_gpio(void) 45ed09a554Srev13@wp.pl { 46ed09a554Srev13@wp.pl int i; 47ed09a554Srev13@wp.pl int rv = 0; 48ed09a554Srev13@wp.pl 4960570df1Skunhuahuang for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { 5060570df1Skunhuahuang rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); 51ed09a554Srev13@wp.pl if (rv) 52ed09a554Srev13@wp.pl goto out; 53ed09a554Srev13@wp.pl } 54ed09a554Srev13@wp.pl 55ed09a554Srev13@wp.pl out: 56ed09a554Srev13@wp.pl return rv; 57ed09a554Srev13@wp.pl } 58ed09a554Srev13@wp.pl 59ed09a554Srev13@wp.pl const struct stm32_gpio_ctl gpio_ctl_fmc = { 60ed09a554Srev13@wp.pl .mode = STM32_GPIO_MODE_AF, 61ed09a554Srev13@wp.pl .otype = STM32_GPIO_OTYPE_PP, 62ed09a554Srev13@wp.pl .speed = STM32_GPIO_SPEED_100M, 63ed09a554Srev13@wp.pl .pupd = STM32_GPIO_PUPD_NO, 64ed09a554Srev13@wp.pl .af = STM32_GPIO_AF12 65ed09a554Srev13@wp.pl }; 66ed09a554Srev13@wp.pl 67ed09a554Srev13@wp.pl static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { 68ed09a554Srev13@wp.pl /* Chip is LQFP144, see DM00077036.pdf for details */ 69ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ 70ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ 71ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ 72ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ 73ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ 74ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ 75ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ 76ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ 77ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ 78ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ 79ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ 80ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ 81ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ 82ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ 83ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ 84ed09a554Srev13@wp.pl {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ 85ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ 86ed09a554Srev13@wp.pl {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ 87ed09a554Srev13@wp.pl {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ 88ed09a554Srev13@wp.pl {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ 89ed09a554Srev13@wp.pl {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ 90ed09a554Srev13@wp.pl {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ 91ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ 92ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ 93ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ 94ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ 95ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ 96ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ 97ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ 98ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ 99ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ 100ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ 101ed09a554Srev13@wp.pl {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */ 102ed09a554Srev13@wp.pl {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ 103ed09a554Srev13@wp.pl {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ 104ed09a554Srev13@wp.pl {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */ 105ed09a554Srev13@wp.pl {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */ 106ed09a554Srev13@wp.pl {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ 107ed09a554Srev13@wp.pl }; 108ed09a554Srev13@wp.pl 109ed09a554Srev13@wp.pl static int fmc_setup_gpio(void) 110ed09a554Srev13@wp.pl { 111ed09a554Srev13@wp.pl int rv = 0; 112ed09a554Srev13@wp.pl int i; 113ed09a554Srev13@wp.pl 114ed09a554Srev13@wp.pl for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { 115ed09a554Srev13@wp.pl rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], 116ed09a554Srev13@wp.pl &gpio_ctl_fmc); 117ed09a554Srev13@wp.pl if (rv) 118ed09a554Srev13@wp.pl goto out; 119ed09a554Srev13@wp.pl } 120ed09a554Srev13@wp.pl 121ed09a554Srev13@wp.pl out: 122ed09a554Srev13@wp.pl return rv; 123ed09a554Srev13@wp.pl } 124ed09a554Srev13@wp.pl 125ed09a554Srev13@wp.pl /* 126ed09a554Srev13@wp.pl * STM32 RCC FMC specific definitions 127ed09a554Srev13@wp.pl */ 128ed09a554Srev13@wp.pl #define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */ 129ed09a554Srev13@wp.pl 130ed09a554Srev13@wp.pl static inline u32 _ns2clk(u32 ns, u32 freq) 131ed09a554Srev13@wp.pl { 132ed09a554Srev13@wp.pl u32 tmp = freq/1000000; 133ed09a554Srev13@wp.pl return (tmp * ns) / 1000; 134ed09a554Srev13@wp.pl } 135ed09a554Srev13@wp.pl 136ed09a554Srev13@wp.pl #define NS2CLK(ns) (_ns2clk(ns, freq)) 137ed09a554Srev13@wp.pl 138ed09a554Srev13@wp.pl /* 139ed09a554Srev13@wp.pl * Following are timings for IS42S16400J, from corresponding datasheet 140ed09a554Srev13@wp.pl */ 141ed09a554Srev13@wp.pl #define SDRAM_CAS 3 /* 3 cycles */ 142ed09a554Srev13@wp.pl #define SDRAM_NB 1 /* Number of banks */ 143ed09a554Srev13@wp.pl #define SDRAM_MWID 1 /* 16 bit memory */ 144ed09a554Srev13@wp.pl 145ed09a554Srev13@wp.pl #define SDRAM_NR 0x1 /* 12-bit row */ 146ed09a554Srev13@wp.pl #define SDRAM_NC 0x0 /* 8-bit col */ 147ed09a554Srev13@wp.pl #define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ 148ed09a554Srev13@wp.pl #define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ 149ed09a554Srev13@wp.pl 150ed09a554Srev13@wp.pl #define SDRAM_TRRD (NS2CLK(14) - 1) 151ed09a554Srev13@wp.pl #define SDRAM_TRCD (NS2CLK(15) - 1) 152ed09a554Srev13@wp.pl #define SDRAM_TRP (NS2CLK(15) - 1) 153ed09a554Srev13@wp.pl #define SDRAM_TRAS (NS2CLK(42) - 1) 154ed09a554Srev13@wp.pl #define SDRAM_TRC (NS2CLK(63) - 1) 155ed09a554Srev13@wp.pl #define SDRAM_TRFC (NS2CLK(63) - 1) 156ed09a554Srev13@wp.pl #define SDRAM_TCDL (1 - 1) 157ed09a554Srev13@wp.pl #define SDRAM_TRDL (2 - 1) 158ed09a554Srev13@wp.pl #define SDRAM_TBDL (1 - 1) 159ed09a554Srev13@wp.pl #define SDRAM_TREF 1386 160ed09a554Srev13@wp.pl #define SDRAM_TCCD (1 - 1) 161ed09a554Srev13@wp.pl 162ed09a554Srev13@wp.pl #define SDRAM_TXSR (NS2CLK(70) - 1)/* Row cycle time after precharge */ 163ed09a554Srev13@wp.pl #define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */ 164ed09a554Srev13@wp.pl 165ed09a554Srev13@wp.pl /* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */ 166ed09a554Srev13@wp.pl #define SDRAM_TWR max(\ 167ed09a554Srev13@wp.pl (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \ 168ed09a554Srev13@wp.pl (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\ 169ed09a554Srev13@wp.pl ) 170ed09a554Srev13@wp.pl 171ed09a554Srev13@wp.pl #define SDRAM_MODE_BL_SHIFT 0 172ed09a554Srev13@wp.pl #define SDRAM_MODE_CAS_SHIFT 4 173ed09a554Srev13@wp.pl #define SDRAM_MODE_BL 0 174ed09a554Srev13@wp.pl #define SDRAM_MODE_CAS SDRAM_CAS 175ed09a554Srev13@wp.pl 176ed09a554Srev13@wp.pl int dram_init(void) 177ed09a554Srev13@wp.pl { 178ed09a554Srev13@wp.pl u32 freq; 179ed09a554Srev13@wp.pl int rv; 180ed09a554Srev13@wp.pl 181ed09a554Srev13@wp.pl rv = fmc_setup_gpio(); 182ed09a554Srev13@wp.pl if (rv) 183ed09a554Srev13@wp.pl return rv; 184ed09a554Srev13@wp.pl 185ed09a554Srev13@wp.pl setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC); 186ed09a554Srev13@wp.pl 187ed09a554Srev13@wp.pl /* 188ed09a554Srev13@wp.pl * Get frequency for NS2CLK calculation. 189ed09a554Srev13@wp.pl */ 190ed09a554Srev13@wp.pl freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; 191ed09a554Srev13@wp.pl 192ed09a554Srev13@wp.pl writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 193ed09a554Srev13@wp.pl | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 194ed09a554Srev13@wp.pl | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 195ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdcr1); 196ed09a554Srev13@wp.pl 197ed09a554Srev13@wp.pl writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 198ed09a554Srev13@wp.pl | SDRAM_CAS << FMC_SDCR_CAS_SHIFT 199ed09a554Srev13@wp.pl | SDRAM_NB << FMC_SDCR_NB_SHIFT 200ed09a554Srev13@wp.pl | SDRAM_MWID << FMC_SDCR_MWID_SHIFT 201ed09a554Srev13@wp.pl | SDRAM_NR << FMC_SDCR_NR_SHIFT 202ed09a554Srev13@wp.pl | SDRAM_NC << FMC_SDCR_NC_SHIFT 203ed09a554Srev13@wp.pl | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 204ed09a554Srev13@wp.pl | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 205ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdcr2); 206ed09a554Srev13@wp.pl 207ed09a554Srev13@wp.pl writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT 208ed09a554Srev13@wp.pl | SDRAM_TRC << FMC_SDTR_TRC_SHIFT, 209ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdtr1); 210ed09a554Srev13@wp.pl 211ed09a554Srev13@wp.pl writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT 212ed09a554Srev13@wp.pl | SDRAM_TRP << FMC_SDTR_TRP_SHIFT 213ed09a554Srev13@wp.pl | SDRAM_TWR << FMC_SDTR_TWR_SHIFT 214ed09a554Srev13@wp.pl | SDRAM_TRC << FMC_SDTR_TRC_SHIFT 215ed09a554Srev13@wp.pl | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT 216ed09a554Srev13@wp.pl | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT 217ed09a554Srev13@wp.pl | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, 218ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdtr2); 219ed09a554Srev13@wp.pl 220ed09a554Srev13@wp.pl writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK, 221ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdcmr); 222ed09a554Srev13@wp.pl 223ed09a554Srev13@wp.pl udelay(200); /* 200 us delay, page 10, "Power-Up" */ 224ed09a554Srev13@wp.pl FMC_BUSY_WAIT(); 225ed09a554Srev13@wp.pl 226ed09a554Srev13@wp.pl writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE, 227ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdcmr); 228ed09a554Srev13@wp.pl 229ed09a554Srev13@wp.pl udelay(100); 230ed09a554Srev13@wp.pl FMC_BUSY_WAIT(); 231ed09a554Srev13@wp.pl 232ed09a554Srev13@wp.pl writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH 233ed09a554Srev13@wp.pl | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); 234ed09a554Srev13@wp.pl 235ed09a554Srev13@wp.pl udelay(100); 236ed09a554Srev13@wp.pl FMC_BUSY_WAIT(); 237ed09a554Srev13@wp.pl 238ed09a554Srev13@wp.pl writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 239ed09a554Srev13@wp.pl | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) 240ed09a554Srev13@wp.pl << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 241ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdcmr); 242ed09a554Srev13@wp.pl 243ed09a554Srev13@wp.pl udelay(100); 244ed09a554Srev13@wp.pl 245ed09a554Srev13@wp.pl FMC_BUSY_WAIT(); 246ed09a554Srev13@wp.pl 247ed09a554Srev13@wp.pl writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL, 248ed09a554Srev13@wp.pl &STM32_SDRAM_FMC->sdcmr); 249ed09a554Srev13@wp.pl 250ed09a554Srev13@wp.pl FMC_BUSY_WAIT(); 251ed09a554Srev13@wp.pl 252ed09a554Srev13@wp.pl /* Refresh timer */ 253ed09a554Srev13@wp.pl writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); 254ed09a554Srev13@wp.pl 255ed09a554Srev13@wp.pl /* 256ed09a554Srev13@wp.pl * Fill in global info with description of SRAM configuration 257ed09a554Srev13@wp.pl */ 258ed09a554Srev13@wp.pl gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; 259ed09a554Srev13@wp.pl gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; 260ed09a554Srev13@wp.pl 261ed09a554Srev13@wp.pl gd->ram_size = CONFIG_SYS_RAM_SIZE; 262ed09a554Srev13@wp.pl 263ed09a554Srev13@wp.pl return rv; 264ed09a554Srev13@wp.pl } 265ed09a554Srev13@wp.pl 266ed09a554Srev13@wp.pl u32 get_board_rev(void) 267ed09a554Srev13@wp.pl { 268ed09a554Srev13@wp.pl return 0; 269ed09a554Srev13@wp.pl } 270ed09a554Srev13@wp.pl 271ed09a554Srev13@wp.pl int board_early_init_f(void) 272ed09a554Srev13@wp.pl { 273ed09a554Srev13@wp.pl int res; 274ed09a554Srev13@wp.pl 27560570df1Skunhuahuang res = uart_setup_gpio(); 276ed09a554Srev13@wp.pl if (res) 277ed09a554Srev13@wp.pl return res; 278ed09a554Srev13@wp.pl 279ed09a554Srev13@wp.pl return 0; 280ed09a554Srev13@wp.pl } 281ed09a554Srev13@wp.pl 282ed09a554Srev13@wp.pl int board_init(void) 283ed09a554Srev13@wp.pl { 284ed09a554Srev13@wp.pl gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 285ed09a554Srev13@wp.pl 286ed09a554Srev13@wp.pl return 0; 287ed09a554Srev13@wp.pl } 288*089fddfdSAntonio Borneo 289*089fddfdSAntonio Borneo #ifdef CONFIG_MISC_INIT_R 290*089fddfdSAntonio Borneo int misc_init_r(void) 291*089fddfdSAntonio Borneo { 292*089fddfdSAntonio Borneo char serialno[25]; 293*089fddfdSAntonio Borneo uint32_t u_id_low, u_id_mid, u_id_high; 294*089fddfdSAntonio Borneo 295*089fddfdSAntonio Borneo if (!getenv("serial#")) { 296*089fddfdSAntonio Borneo u_id_low = readl(&STM32_U_ID->u_id_low); 297*089fddfdSAntonio Borneo u_id_mid = readl(&STM32_U_ID->u_id_mid); 298*089fddfdSAntonio Borneo u_id_high = readl(&STM32_U_ID->u_id_high); 299*089fddfdSAntonio Borneo sprintf(serialno, "%08x%08x%08x", 300*089fddfdSAntonio Borneo u_id_high, u_id_mid, u_id_low); 301*089fddfdSAntonio Borneo setenv("serial#", serialno); 302*089fddfdSAntonio Borneo } 303*089fddfdSAntonio Borneo 304*089fddfdSAntonio Borneo return 0; 305*089fddfdSAntonio Borneo } 306*089fddfdSAntonio Borneo #endif 307