1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * Copyright (C) 2012 Stefan Roese <sr@denx.de> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <micrel.h> 12 #include <nand.h> 13 #include <netdev.h> 14 #include <phy.h> 15 #include <rtc.h> 16 #include <asm/io.h> 17 #include <asm/mach-types.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/arch/spr_defs.h> 20 #include <asm/arch/spr_misc.h> 21 #include <linux/mtd/fsmc_nand.h> 22 #include "fpga.h" 23 24 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; 25 26 int board_init(void) 27 { 28 /* 29 * X600 is equipped with an M41T82 RTC. This RTC has the 30 * HT bit (Halt Update), which needs to be cleared upon 31 * power-up. Otherwise the RTC is halted. 32 */ 33 rtc_reset(); 34 35 return spear_board_init(MACH_TYPE_SPEAR600); 36 } 37 38 int board_late_init(void) 39 { 40 /* 41 * Monitor and env protection on by default 42 */ 43 flash_protect(FLAG_PROTECT_SET, 44 CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 45 CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN + 46 2 * CONFIG_ENV_SECT_SIZE - 1, 47 &flash_info[0]); 48 49 /* Init FPGA subsystem */ 50 x600_init_fpga(); 51 52 return 0; 53 } 54 55 /* 56 * board_nand_init - Board specific NAND initialization 57 * @nand: mtd private chip structure 58 * 59 * Called by nand_init_chip to initialize the board specific functions 60 */ 61 62 void board_nand_init(void) 63 { 64 struct misc_regs *const misc_regs_p = 65 (struct misc_regs *)CONFIG_SPEAR_MISCBASE; 66 struct nand_chip *nand = &nand_chip[0]; 67 68 if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) 69 fsmc_nand_init(nand); 70 } 71 72 int board_phy_config(struct phy_device *phydev) 73 { 74 unsigned short id1, id2; 75 76 /* check whether KSZ9031 or AR8035 has to be configured */ 77 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); 78 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); 79 80 if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { 81 /* PHY configuration for Micrel KSZ9031 */ 82 printf("PHY KSZ9031 detected - "); 83 84 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); 85 86 /* control data pad skew - devaddr = 0x02, register = 0x04 */ 87 ksz9031_phy_extended_write(phydev, 0x02, 88 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 89 MII_KSZ9031_MOD_DATA_NO_POST_INC, 90 0x0000); 91 /* rx data pad skew - devaddr = 0x02, register = 0x05 */ 92 ksz9031_phy_extended_write(phydev, 0x02, 93 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 94 MII_KSZ9031_MOD_DATA_NO_POST_INC, 95 0x0000); 96 /* tx data pad skew - devaddr = 0x02, register = 0x05 */ 97 ksz9031_phy_extended_write(phydev, 0x02, 98 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 99 MII_KSZ9031_MOD_DATA_NO_POST_INC, 100 0x0000); 101 /* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */ 102 ksz9031_phy_extended_write(phydev, 0x02, 103 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 104 MII_KSZ9031_MOD_DATA_NO_POST_INC, 105 0x03FF); 106 } else { 107 /* PHY configuration for Vitesse VSC8641 */ 108 printf("PHY VSC8641 detected - "); 109 110 /* Extended PHY control 1, select GMII */ 111 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); 112 113 /* Software reset necessary after GMII mode selction */ 114 phy_reset(phydev); 115 116 /* Enable extended page register access */ 117 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); 118 119 /* 17e: Enhanced LED behavior, needs to be written twice */ 120 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); 121 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); 122 123 /* 16e: Enhanced LED method select */ 124 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); 125 126 /* Disable extended page register access */ 127 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); 128 129 /* Enable clock output pin */ 130 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); 131 } 132 133 if (phydev->drv->config) 134 phydev->drv->config(phydev); 135 136 return 0; 137 } 138 139 int board_eth_init(bd_t *bis) 140 { 141 int ret = 0; 142 143 if (designware_initialize(CONFIG_SPEAR_ETHBASE, 144 PHY_INTERFACE_MODE_GMII) >= 0) 145 ret++; 146 147 return ret; 148 } 149