1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * Copyright (C) 2012 Stefan Roese <sr@denx.de> 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <nand.h> 28 #include <netdev.h> 29 #include <phy.h> 30 #include <rtc.h> 31 #include <asm/io.h> 32 #include <asm/arch/hardware.h> 33 #include <asm/arch/spr_defs.h> 34 #include <asm/arch/spr_misc.h> 35 #include <linux/mtd/fsmc_nand.h> 36 #include "fpga.h" 37 38 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; 39 40 int board_init(void) 41 { 42 /* 43 * X600 is equipped with an M41T82 RTC. This RTC has the 44 * HT bit (Halt Update), which needs to be cleared upon 45 * power-up. Otherwise the RTC is halted. 46 */ 47 rtc_reset(); 48 49 return spear_board_init(MACH_TYPE_SPEAR600); 50 } 51 52 int board_late_init(void) 53 { 54 /* 55 * Monitor and env protection on by default 56 */ 57 flash_protect(FLAG_PROTECT_SET, 58 CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 59 CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN + 60 2 * CONFIG_ENV_SECT_SIZE - 1, 61 &flash_info[0]); 62 63 /* Init FPGA subsystem */ 64 x600_init_fpga(); 65 66 return 0; 67 } 68 69 /* 70 * board_nand_init - Board specific NAND initialization 71 * @nand: mtd private chip structure 72 * 73 * Called by nand_init_chip to initialize the board specific functions 74 */ 75 76 void board_nand_init(void) 77 { 78 struct misc_regs *const misc_regs_p = 79 (struct misc_regs *)CONFIG_SPEAR_MISCBASE; 80 struct nand_chip *nand = &nand_chip[0]; 81 82 if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) 83 fsmc_nand_init(nand); 84 } 85 86 int designware_board_phy_init(struct eth_device *dev, int phy_addr, 87 int (*mii_write)(struct eth_device *, u8, u8, u16), 88 int dw_reset_phy(struct eth_device *)) 89 { 90 /* Extended PHY control 1, select GMII */ 91 mii_write(dev, phy_addr, 23, 0x0020); 92 93 /* Software reset necessary after GMII mode selction */ 94 dw_reset_phy(dev); 95 96 /* Enable extended page register access */ 97 mii_write(dev, phy_addr, 31, 0x0001); 98 99 /* 17e: Enhanced LED behavior, needs to be written twice */ 100 mii_write(dev, phy_addr, 17, 0x09ff); 101 mii_write(dev, phy_addr, 17, 0x09ff); 102 103 /* 16e: Enhanced LED method select */ 104 mii_write(dev, phy_addr, 16, 0xe0ea); 105 106 /* Disable extended page register access */ 107 mii_write(dev, phy_addr, 31, 0x0000); 108 109 /* Enable clock output pin */ 110 mii_write(dev, phy_addr, 18, 0x0049); 111 112 return 0; 113 } 114 115 int board_eth_init(bd_t *bis) 116 { 117 int ret = 0; 118 119 if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, 120 PHY_INTERFACE_MODE_GMII) >= 0) 121 ret++; 122 123 return ret; 124 } 125