1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * Copyright (C) 2012 Stefan Roese <sr@denx.de> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <micrel.h> 12 #include <nand.h> 13 #include <netdev.h> 14 #include <phy.h> 15 #include <rtc.h> 16 #include <asm/io.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/spr_defs.h> 19 #include <asm/arch/spr_misc.h> 20 #include <linux/mtd/fsmc_nand.h> 21 #include "fpga.h" 22 23 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; 24 25 int board_init(void) 26 { 27 /* 28 * X600 is equipped with an M41T82 RTC. This RTC has the 29 * HT bit (Halt Update), which needs to be cleared upon 30 * power-up. Otherwise the RTC is halted. 31 */ 32 rtc_reset(); 33 34 return spear_board_init(MACH_TYPE_SPEAR600); 35 } 36 37 int board_late_init(void) 38 { 39 /* 40 * Monitor and env protection on by default 41 */ 42 flash_protect(FLAG_PROTECT_SET, 43 CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 44 CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN + 45 2 * CONFIG_ENV_SECT_SIZE - 1, 46 &flash_info[0]); 47 48 /* Init FPGA subsystem */ 49 x600_init_fpga(); 50 51 return 0; 52 } 53 54 /* 55 * board_nand_init - Board specific NAND initialization 56 * @nand: mtd private chip structure 57 * 58 * Called by nand_init_chip to initialize the board specific functions 59 */ 60 61 void board_nand_init(void) 62 { 63 struct misc_regs *const misc_regs_p = 64 (struct misc_regs *)CONFIG_SPEAR_MISCBASE; 65 struct nand_chip *nand = &nand_chip[0]; 66 67 if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) 68 fsmc_nand_init(nand); 69 } 70 71 int board_phy_config(struct phy_device *phydev) 72 { 73 unsigned short id1, id2; 74 75 /* check whether KSZ9031 or AR8035 has to be configured */ 76 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); 77 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); 78 79 if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { 80 /* PHY configuration for Micrel KSZ9031 */ 81 printf("PHY KSZ9031 detected - "); 82 83 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); 84 85 /* control data pad skew - devaddr = 0x02, register = 0x04 */ 86 ksz9031_phy_extended_write(phydev, 0x02, 87 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 88 MII_KSZ9031_MOD_DATA_NO_POST_INC, 89 0x0000); 90 /* rx data pad skew - devaddr = 0x02, register = 0x05 */ 91 ksz9031_phy_extended_write(phydev, 0x02, 92 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 93 MII_KSZ9031_MOD_DATA_NO_POST_INC, 94 0x0000); 95 /* tx data pad skew - devaddr = 0x02, register = 0x05 */ 96 ksz9031_phy_extended_write(phydev, 0x02, 97 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 98 MII_KSZ9031_MOD_DATA_NO_POST_INC, 99 0x0000); 100 /* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */ 101 ksz9031_phy_extended_write(phydev, 0x02, 102 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 103 MII_KSZ9031_MOD_DATA_NO_POST_INC, 104 0x03FF); 105 } else { 106 /* PHY configuration for Vitesse VSC8641 */ 107 printf("PHY VSC8641 detected - "); 108 109 /* Extended PHY control 1, select GMII */ 110 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); 111 112 /* Software reset necessary after GMII mode selction */ 113 phy_reset(phydev); 114 115 /* Enable extended page register access */ 116 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); 117 118 /* 17e: Enhanced LED behavior, needs to be written twice */ 119 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); 120 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); 121 122 /* 16e: Enhanced LED method select */ 123 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); 124 125 /* Disable extended page register access */ 126 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); 127 128 /* Enable clock output pin */ 129 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); 130 } 131 132 if (phydev->drv->config) 133 phydev->drv->config(phydev); 134 135 return 0; 136 } 137 138 int board_eth_init(bd_t *bis) 139 { 140 int ret = 0; 141 142 if (designware_initialize(CONFIG_SPEAR_ETHBASE, 143 PHY_INTERFACE_MODE_GMII) >= 0) 144 ret++; 145 146 return ret; 147 } 148