1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * Copyright (C) 2012 Stefan Roese <sr@denx.de> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <nand.h> 12 #include <netdev.h> 13 #include <phy.h> 14 #include <rtc.h> 15 #include <asm/io.h> 16 #include <asm/arch/hardware.h> 17 #include <asm/arch/spr_defs.h> 18 #include <asm/arch/spr_misc.h> 19 #include <linux/mtd/fsmc_nand.h> 20 #include "fpga.h" 21 22 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; 23 24 int board_init(void) 25 { 26 /* 27 * X600 is equipped with an M41T82 RTC. This RTC has the 28 * HT bit (Halt Update), which needs to be cleared upon 29 * power-up. Otherwise the RTC is halted. 30 */ 31 rtc_reset(); 32 33 return spear_board_init(MACH_TYPE_SPEAR600); 34 } 35 36 int board_late_init(void) 37 { 38 /* 39 * Monitor and env protection on by default 40 */ 41 flash_protect(FLAG_PROTECT_SET, 42 CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 43 CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN + 44 2 * CONFIG_ENV_SECT_SIZE - 1, 45 &flash_info[0]); 46 47 /* Init FPGA subsystem */ 48 x600_init_fpga(); 49 50 return 0; 51 } 52 53 /* 54 * board_nand_init - Board specific NAND initialization 55 * @nand: mtd private chip structure 56 * 57 * Called by nand_init_chip to initialize the board specific functions 58 */ 59 60 void board_nand_init(void) 61 { 62 struct misc_regs *const misc_regs_p = 63 (struct misc_regs *)CONFIG_SPEAR_MISCBASE; 64 struct nand_chip *nand = &nand_chip[0]; 65 66 if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) 67 fsmc_nand_init(nand); 68 } 69 70 int designware_board_phy_init(struct eth_device *dev, int phy_addr, 71 int (*mii_write)(struct eth_device *, u8, u8, u16), 72 int dw_reset_phy(struct eth_device *)) 73 { 74 /* Extended PHY control 1, select GMII */ 75 mii_write(dev, phy_addr, 23, 0x0020); 76 77 /* Software reset necessary after GMII mode selction */ 78 dw_reset_phy(dev); 79 80 /* Enable extended page register access */ 81 mii_write(dev, phy_addr, 31, 0x0001); 82 83 /* 17e: Enhanced LED behavior, needs to be written twice */ 84 mii_write(dev, phy_addr, 17, 0x09ff); 85 mii_write(dev, phy_addr, 17, 0x09ff); 86 87 /* 16e: Enhanced LED method select */ 88 mii_write(dev, phy_addr, 16, 0xe0ea); 89 90 /* Disable extended page register access */ 91 mii_write(dev, phy_addr, 31, 0x0000); 92 93 /* Enable clock output pin */ 94 mii_write(dev, phy_addr, 18, 0x0049); 95 96 return 0; 97 } 98 99 int board_eth_init(bd_t *bis) 100 { 101 int ret = 0; 102 103 if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, 104 PHY_INTERFACE_MODE_GMII) >= 0) 105 ret++; 106 107 return ret; 108 } 109